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    TRANSISTOR WITH DIELECTRIC STRESSOR ELEMENT FULLY UNDERLYING THE ACTIVE SEMICONDUCTOR REGION
    1.
    发明申请
    TRANSISTOR WITH DIELECTRIC STRESSOR ELEMENT FULLY UNDERLYING THE ACTIVE SEMICONDUCTOR REGION 失效
    具有完全基于主动半导体区域的电介质压电元件的晶体管

    公开(公告)号：US20070122956A1

    公开(公告)日：2007-05-31

    申请号：US11164632

    申请日：2005-11-30

    申请人： Dureseti Chidambarrao ,  Brian Greene ,  Kern Rim

    发明人： Dureseti Chidambarrao ,  Brian Greene ,  Kern Rim

    IPC分类号： H01L21/8234 ,  H01L31/00 ,  H01L21/336

    CPC分类号： H01L29/7849 ,  H01L21/26513 ,  H01L21/31675 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78654

    摘要： A compressive stress is applied to a channel region of a PFET by structure including a discrete dielectric stressor element that fully underlies the bottom surface of an active semiconductor region in which the source, drain and channel region of the PFET is disposed. In particular, the dielectric stressor element includes a region of collapsed oxide which fully contacts the bottom surface of the active semiconductor region such that it has an area coextensive with an area of the bottom surface. Bird's beak oxide regions at edges of the dielectric stressor element apply an upward force at edges of the dielectric stressor element to impart a compressive stress to the channel region of the PFET.

    摘要翻译： 压缩应力通过结构施加到PFET的沟道区域，其包括完全位于其中设置有PFET的源极，漏极和沟道区域的有源半导体区域的底表面的离散介电应激元件。 特别地，介电应力元件包括与活性半导体区域的底表面完全接触的塌陷氧化物区域，使得其具有与底表面的区域共同延伸的区域。 电介质应力元件边缘处的鸟喙氧化物区域在介质应力元件的边缘施加向上的力，以向PFET的沟道区域施加压应力。

    TRANSISTOR WITH DIELECTRIC STRESSOR ELEMENTS
    2.
    发明申请
    TRANSISTOR WITH DIELECTRIC STRESSOR ELEMENTS 失效
    具有介质压力元件的晶体管

    公开(公告)号：US20070096215A1

    公开(公告)日：2007-05-03

    申请号：US11163683

    申请日：2005-10-27

    申请人： Dureseti Chidambarrao ,  Brian Greene ,  Kern Rim

    发明人： Dureseti Chidambarrao ,  Brian Greene ,  Kern Rim

    IPC分类号： H01L29/94 ,  H01L21/8238

    CPC分类号： H01L21/823481 ,  H01L21/76232 ,  H01L21/823412 ,  H01L29/0653 ,  H01L29/7846

    摘要： A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region, and a transverse direction in a direction of a width of the channel region. A dielectric stressor element having a horizontally extending upper surface extends below a portion of the active semiconductor region. The dielectric stressor element shares an edge with the active semiconductor region, the edge extending in a direction away from the upper surface. In particular structures, two or more dielectric stressor elements are provided at locations opposite from each other in the longitudinal and/or transverse directions of the FET.

    摘要翻译： 提供一种芯片，其包括有源半导体区域和具有全部设置在有源半导体区域内的沟道区域，源极区域和漏极区域的场效应晶体管（“FET”）。 FET在通道区域的长度方向和沟道区域的宽度方向的横向方向上具有长度方向。 具有水平延伸的上表面的介电应激元件在有源半导体区域的一部分的下方延伸。 电介质应力元件与有源半导体区域共享边缘，边缘沿远离上表面的方向延伸。 在特定结构中，在FET的纵向和/或横向方向上彼此相对的位置处提供两个或更多个介电应激元件。

    PLANAR ULTRA-THIN SEMICONDUCTOR-ON-INSULATOR CHANNEL MOSFET WITH EMBEDDED SOURCE/DRAIN
    3.
    发明申请
    PLANAR ULTRA-THIN SEMICONDUCTOR-ON-INSULATOR CHANNEL MOSFET WITH EMBEDDED SOURCE/DRAIN 审中-公开
    具有嵌入式源/漏极的平面超薄半导体绝缘体通道MOSFET

    公开(公告)号：US20070069300A1

    公开(公告)日：2007-03-29

    申请号：US11162959

    申请日：2005-09-29

    申请人： Kangguo Cheng ,  Dureseti Chidambarrao ,  Brian Greene ,  Jack Mandelman ,  Kern Rim

    发明人： Kangguo Cheng ,  Dureseti Chidambarrao ,  Brian Greene ,  Jack Mandelman ,  Kern Rim

    IPC分类号： H01L29/94

    CPC分类号： H01L21/2652 ,  H01L21/02203 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/31662 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

    摘要： A MOSFET structure includes a planar semiconductor substrate, a gate dielectric and a gate. An ultra-thin (UT) semiconductor-on-insulator channel extends to a first depth below the top surface of the substrate and is self-aligned to and is laterally coextensive with the gate. Source-drain regions, extend to a second depth greater than the first depth below the top surface, and are self-aligned to the UT channel region. A first BOX region extends across the entire structure, and vertically from the second depth to a third depth below the top surface. An upper portion of a second BOX region under the UT channel region is self-aligned to and is laterally coextensive with the gate, and extends vertically from the first depth to a third depth below the top surface, and where the third depth is greater than the second depth.

    摘要翻译： MOSFET结构包括平面半导体衬底，栅极电介质和栅极。 超薄（UT）绝缘体上半导体通道延伸到衬底的顶表面下方的第一深度，并且与栅极自对准并且横向共延伸。 源极 - 漏极区域延伸到大于顶部表面下方的第一深度的第二深度，并且与UT沟道区域自对准。 第一BOX区域跨越整个结构延伸，并且从第二深度垂直延伸到顶表面下方的第三深度。 在UT通道区域下面的第二BOX区域的上部自对准并且与栅极横向共同延伸，并且从第一深度垂直延伸到顶表面下方的第三深度，并且其中第三深度大于 第二个深度。

    TRANSISTOR HAVING DIELECTRIC STRESSOR ELEMENTS AT DIFFERENT DEPTHS FROM A SEMICONDUCTOR SURFACE FOR APPLYING SHEAR STRESS
    4.
    发明申请
    TRANSISTOR HAVING DIELECTRIC STRESSOR ELEMENTS AT DIFFERENT DEPTHS FROM A SEMICONDUCTOR SURFACE FOR APPLYING SHEAR STRESS 失效
    具有用于施加剪切应力的半导体表面的不同深度的介电压力元件的晶体管

    公开(公告)号：US20070114632A1

    公开(公告)日：2007-05-24

    申请号：US11164373

    申请日：2005-11-21

    申请人： Dureseti Chidambarrao ,  Brian Greene ,  Kern Rim

    发明人： Dureseti Chidambarrao ,  Brian Greene ,  Kern Rim

    IPC分类号： H01L29/00 ,  H01L21/8238

    CPC分类号： H01L21/823878 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7846

    摘要： A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region, and a transverse direction in a direction of a width of the channel region. A buried dielectric stressor element has a horizontally extending upper surface at a first depth below a major surface of a portion of the active semiconductor region, such as an east portion of the active semiconductor region. A surface dielectric stressor element is disposed laterally adjacent to the active semiconductor region at the major surface of the active semiconductor region. The surface dielectric stressor element extends from the major surface to a second depth not substantially greater than the first depth. The stresses applied by the buried and surface dielectric stressor elements cooperate together to apply a shear stress to the channel region of the FET.

    摘要翻译： 提供一种芯片，其包括有源半导体区域和具有全部设置在有源半导体区域内的沟道区域，源极区域和漏极区域的场效应晶体管（“FET”）。 FET在通道区域的长度方向和沟道区域的宽度方向的横向方向上具有长度方向。 掩埋介质应力元件在有源半导体区域的一部分的主表面下方的第一深度（例如有源半导体区域的东部）处具有水平延伸的上表面。 在有源半导体区域的主表面处，表面介电应力元件横向邻近有源半导体区域设置。 表面介电应力元件从主表面延伸到不大于第一深度的第二深度。 由埋层和表面介电应力元件施加的应力协同工作，对FET的沟道区施加剪切应力。

    TRANSISTOR HAVING DIELECTRIC STRESSOR ELEMENTS FOR APPLYING IN-PLANE SHEAR STRESS
    5.
    发明申请
    TRANSISTOR HAVING DIELECTRIC STRESSOR ELEMENTS FOR APPLYING IN-PLANE SHEAR STRESS 有权
    具有用于施加平面内剪应力的电介质压力元件的晶体管

    公开(公告)号：US20070096223A1

    公开(公告)日：2007-05-03

    申请号：US11163686

    申请日：2005-10-27

    申请人： Dureseti Chidambarrao ,  Brian Greene ,  Kern Rim

    发明人： Dureseti Chidambarrao ,  Brian Greene ,  Kern Rim

    IPC分类号： H01L27/12

    CPC分类号： H01L29/1083 ,  H01L21/02203 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/02337 ,  H01L21/31675 ,  H01L29/7833 ,  H01L29/7846

    摘要： A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region, and a transverse direction in a direction of a width of the channel region. A first dielectric stressor element having a horizontally extending upper surface extends below a portion of the active semiconductor region, such as a northwest portion of the active semiconductor region. A second dielectric stressor element having a horizontally extending upper surface extends below a second portion of the active semiconductor region, such as a southeast portion of the active semiconductor region. Each of the first and second dielectric stressor elements shares an edge with the active semiconductor region, the edges extending in directions away from the upper surface.

    摘要翻译： 提供一种芯片，其包括有源半导体区域和具有全部设置在有源半导体区域内的沟道区域，源极区域和漏极区域的场效应晶体管（“FET”）。 FET在通道区域的长度方向和沟道区域的宽度方向的横向方向上具有长度方向。 具有水平延伸的上表面的第一介电应激元件在有源半导体区域的一部分的下方延伸，例如有源半导体区域的西北部分。 具有水平延伸的上表面的第二介电应激元件在有源半导体区域的第二部分的下方延伸，例如有源半导体区域的东南部分。 第一和第二介电应力元件中的每一个与有源半导体区域共享边缘，边缘沿远离上表面的方向延伸。

    MOSFET structure with high mechanical stress in the channel
    6.
    发明授权
    MOSFET structure with high mechanical stress in the channel 有权
    MOSFET结构在通道中具有高机械应力

    公开(公告)号：US07002209B2

    公开(公告)日：2006-02-21

    申请号：US10851830

    申请日：2004-05-21

    申请人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Brian Greene ,  Kern Rim ,  Haining S. Yang

    发明人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Brian Greene ,  Kern Rim ,  Haining S. Yang

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

    摘要： The present invention provides a semiconducting device including at least one gate region including a gate conductor located on a surface of a substrate, the substrate having an exposed surface adjacent the gate region; a silicide contact located adjacent the exposed surface; and a stress inducing liner located on the silicide contact, the exposed surface of the substrate adjacent to the gate region and the at least one gate region, wherein the stress inducing liner provides a stress to a device channel portion of the substrate underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 200 MPa to about 2000 MPa. The present invention also provides a method for forming the above-described semiconducting device.

    摘要翻译： 本发明提供了一种半导体器件，其包括至少一个栅极区域，该栅极区域包括位于衬底表面上的栅极导体，该衬底具有邻近栅极区域的暴露表面; 位于暴露表面附近的硅化物触点; 以及位于所述硅化物接触处的所述应力诱导衬垫，所述衬底的与所述栅极区域和所述至少一个栅极区域相邻的暴露表面，其中所述应力诱导衬垫向所述栅极区域下方的衬底的器件沟道部分施加应力 。 在器件通道上产生的应力是约200MPa至约2000MPa的纵向应力。 本发明还提供了形成上述半导体器件的方法。

    MOSFET structure with high mechanical stress in the channel
    7.
    发明申请
    MOSFET structure with high mechanical stress in the channel 有权
    MOSFET结构在通道中具有高机械应力

    公开(公告)号：US20050260808A1

    公开(公告)日：2005-11-24

    申请号：US10851830

    申请日：2004-05-21

    申请人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Brian Greene ,  Kern Rim ,  Haining Yang

    发明人： Xiangdong Chen ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Brian Greene ,  Kern Rim ,  Haining Yang

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

    摘要： The present invention provides a semiconducting device including at least one gate region including a gate conductor located on a surface of a substrate, the substrate having an exposed surface adjacent the gate region; a silicide contact located adjacent the exposed surface; and a stress inducing liner located on the silicide contact, the exposed surface of the substrate adjacent to the gate region and the at least one gate region, wherein the stress inducing liner provides a stress to a device channel portion of the substrate underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 200 MPa to about 2000 MPa. The present invention also provides a method for forming the above-described semiconducting device.

    摘要翻译： 本发明提供了一种半导体器件，其包括至少一个栅极区域，该栅极区域包括位于衬底表面上的栅极导体，该衬底具有邻近栅极区域的暴露表面; 位于暴露表面附近的硅化物触点; 以及位于所述硅化物接触处的所述应力诱导衬垫，所述衬底的与所述栅极区域和所述至少一个栅极区域相邻的暴露表面，其中所述应力诱导衬垫向所述栅极区域下方的衬底的器件沟道部分施加应力 。 在器件通道上产生的应力是约200MPa至约2000MPa的纵向应力。 本发明还提供了形成上述半导体器件的方法。

    FORMATION OF IMPROVED SOI SUBSTRATES USING BULK SEMICONDUCTOR WAFERS
    9.
    发明申请
    FORMATION OF IMPROVED SOI SUBSTRATES USING BULK SEMICONDUCTOR WAFERS 有权
    使用块状半导体波形形成改进的SOI衬底

    公开(公告)号：US20110147885A1

    公开(公告)日：2011-06-23

    申请号：US13037608

    申请日：2011-03-01

    申请人： William K. Henson ,  Dureseti Chidambarrao ,  Kern Rim ,  Hsingjen Wann ,  Hung Y. Ng

    发明人： William K. Henson ,  Dureseti Chidambarrao ,  Kern Rim ,  Hsingjen Wann ,  Hung Y. Ng

    IPC分类号： H01L23/58

    CPC分类号： H01L21/764 ,  H01L21/76283

    摘要： The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.

    摘要翻译： 本发明涉及具有一个或多个器件区域的绝缘体上半导体（SOI）衬底。 每个器件区域至少包括基底半导体衬底层和其间设置有掩埋绝缘体层的半导体器件层，而半导体器件层由一个或多个垂直绝缘柱支撑。 垂直绝缘柱各自优选地具有在基底半导体衬底层和半导体器件层之间延伸的凸缘。 本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，半导体器件层通过气隙与基底半导体衬底层间隔开并由一个或多个垂直绝缘柱支撑。 气隙优选通过选择性地去除位于基底半导体衬底层和半导体器件层之间的牺牲层来形成。