LONG PACKET EXTENSION SIGNALING
    3.
    发明申请

    公开(公告)号:US20210314205A1

    公开(公告)日:2021-10-07

    申请号:US17344201

    申请日:2021-06-10

    IPC分类号: H04L27/26 H04W28/06

    摘要: This disclosure describes systems, methods, and devices related to long packet extension signaling. A device may calculate a residual value based on a duration of a packet extension, a transmit time, and a signal extension time. The device may generate one or more data symbols of a frame to be transmitted to a station device (STA). The device may compare the residual value to a duration of a first data symbol of the one or more data symbols. The device may include a packet extension dis-ambiguity value to the frame based on the comparison. The device may cause to send the frame to the STA.

    LDPC codes with small amount of wiring
    7.
    发明授权
    LDPC codes with small amount of wiring 有权
    具有少量布线的LDPC码

    公开(公告)号:US08464121B2

    公开(公告)日:2013-06-11

    申请号:US12558415

    申请日:2009-09-11

    IPC分类号: H03M13/11 H03M13/27

    摘要: The embodiments herein relate to Low Density Parity Check (LDPC) codes, their corresponding matrices, and with an LDPC decoder architecture used to decode those codes. Embodiments herein relate to methods to generate a set of LDPC codes (typically of different rates) that share their wires as much as possible and therefore reduce the silicon area and ease the routing.

    摘要翻译: 本文的实施例涉及低密度奇偶校验(LDPC)码及其对应的矩阵,以及用于解码这些码的LDPC解码器架构。 本文的实施例涉及生成尽可能多地共享其线的LDPC码集(通常具有不同速率)的方法,并因此减少了硅面积并简化了路由。