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    Adjustment of write timing based on error detection techniques
    1.
    发明授权
    Adjustment of write timing based on error detection techniques 有权
    基于错误检测技术调整写时序

    公开(公告)号：US08862966B2

    公开(公告)日：2014-10-14

    申请号：US12846958

    申请日：2010-07-30

    Applicant: Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger

    Inventor： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger

    IPC: H03M13/00 ,  G06F13/42

    CPC classification number: G06F13/4243

    Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.

    Abstract translation: 提供了一种方法，系统和计算机程序产品，用于基于错误检测功能的结果来调整存储器件中的写入定时。 例如，该方法可以包括基于错误检测功能的结果来确定数据总线上的信号与写入时钟信号之间的写时序窗口。 该方法还可以包括基于写时序窗口调整数据总线上的信号与写时钟信号之间的相位差。 存储器件可以基于调整后的相位差来恢复数据总线上的数据。

    TFT-LCD, manufacturing method and driving method thereof
    2.
    发明授权
    TFT-LCD, manufacturing method and driving method thereof 有权
    TFT-LCD，其制造方法和驱动方法

    公开(公告)号：US08836902B2

    公开(公告)日：2014-09-16

    申请号：US13284216

    申请日：2011-10-28

    Applicant: Jianlei Zhu ,  Xiaoling Xu ,  Jaegeon You

    Inventor： Jianlei Zhu ,  Xiaoling Xu ,  Jaegeon You

    IPC: G02F1/1343 ,  G02F1/1335 ,  G02F1/139

    CPC classification number: G02F1/133512 ,  G02F1/134363 ,  G02F1/1396 ,  G02F2001/134345 ,  G02F2001/134381

    Abstract: Embodiments of the disclosed technology provide a TFT-LCD and manufacturing method and driving method thereof. The TFT-LCD comprises a color filter substrate, an array substrate, and a liquid crystal layer sandwiched between the color filter substrate and the array substrate. A first strip-like electrode and a second strip-like electrode are formed in the area of a black matrix on the color filter substrate, an area surrounded by the first strip-like electrode and the second strip-like electrode comprises at least one sub-pixel area, and the first strip-like electrode and second strip-like electrode are electrically insulated from each other.

    Abstract translation: 所公开技术的实施例提供了TFT-LCD及其制造方法和驱动方法。 TFT-LCD包括滤色器基板，阵列基板和夹在滤色器基板和阵列基板之间的液晶层。 在滤色器基板上的黑矩阵的区域中形成第一带状电极和第二带状电极，由第一条状电极和第二带状电极围绕的区域包括至少一个子 像素区域，并且第一条状电极和第二带状电极彼此电绝缘。

    Localizing neural sources in a brain
    3.
    发明申请
    Localizing neural sources in a brain 有权
    在脑中定位神经源

    公开(公告)号：US20060251303A1

    公开(公告)日：2006-11-09

    申请号：US11372225

    申请日：2006-03-09

    Applicant: Bin He ,  Xiaoling Xu ,  Bobby Xu

    Inventor： Bin He ,  Xiaoling Xu ,  Bobby Xu

    IPC: G06K9/00

    CPC classification number: G06K9/0057 ,  A61B5/04008 ,  A61B5/0476 ,  A61B5/4094

    Abstract: Described herein is a non-invasive determination of locations of neural activity in a brain. In particular, methods and systems have been developed that utilize a FINES algorithm for use in three-dimensional (3-D) dipole source localization to locate neural activity in a brain.

    Abstract translation: 本文描述的是脑内神经活动位置的非侵入性测定。 特别地，已经开发了利用FINES算法用于三维（3-D）偶极子源定位以定位脑中的神经活动的方法和系统。

    Command protocol for adjustment of write timing delay
    5.
    发明授权
    Command protocol for adjustment of write timing delay 有权
    用于调整写时序延迟的命令协议

    公开(公告)号：US08489912B2

    公开(公告)日：2013-07-16

    申请号：US12846972

    申请日：2010-07-30

    Applicant: Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael John Litt

    Inventor： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael John Litt

    IPC: G06F1/04

    CPC classification number: G06F1/14 ,  G06F1/08 ,  G06F13/1689

    Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal.

    Abstract translation: 提供了一种方法，系统和计算机程序产品，用于基于命令协议来调整存储器设备中的写入定时。 例如，该方法可以包括启用写时钟数据恢复（WCDR）操作模式。 该方法还可以包括在WCDR操作模式和存储器件的另一操作模式期间将WCDR数据从处理单元发送到存储器件。 基于WCDR数据中的相移，可以调整数据总线上的信号与写入时钟信号之间的相位差。 此外，该方法可以包括基于数据总线上的信号与写入时钟信号之间调整的相位差在数据总线上传送信号。

    Write data mask method and system
    7.
    发明授权
    Write data mask method and system 有权
    写数据掩码的方法和系统

    公开(公告)号：US08275972B2

    公开(公告)日：2012-09-25

    申请号：US11509143

    申请日：2006-08-23

    Applicant: Xiaoling Xu ,  Warren F. Kruger

    Inventor： Xiaoling Xu ,  Warren F. Kruger

    IPC: G06F12/04

    CPC classification number: G11C7/1006 ,  G11C7/1078 ,  G11C7/1096

    Abstract: In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface.

    Abstract translation: 在各种实施例中，通过在接口的地址线上发送数据掩码来消除专用掩码引脚。 存储器控制器从存储器客户端接收对存储器写入操作的请求，并且根据客户端发送的写入数据掩码确定写入数据的粒度。 如本文所使用的，粒度表示所接收的写数据掩码的每个位适用的写数据量。 在一个实施例中，存储器控制器基于写入数据的粒度生成特定的写入命令和特定的写入数据掩码。 所生成的写入命令通常是可用的多个写入命令中最有效的，但实施例不限于此。 写命令在接口的命令行上传输，写数据掩码在接口的地址线上传输。

    Command Protocol for Adjustment of Write Timing Delay
    8.
    发明申请
    Command Protocol for Adjustment of Write Timing Delay 有权
    用于调整写时序延迟的命令协议

    公开(公告)号：US20110208989A1

    公开(公告)日：2011-08-25

    申请号：US12846972

    申请日：2010-07-30

    Applicant: Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael John Litt

    Inventor： Aaron John Nygren ,  Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan Duc Pham ,  Warren Fritz Kruger ,  Michael John Litt

    IPC: G06F1/08

    CPC classification number: G06F1/14 ,  G06F1/08 ,  G06F13/1689

    Abstract: A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal.

    Abstract translation: 提供了一种方法，系统和计算机程序产品，用于基于命令协议来调整存储器设备中的写入定时。 例如，该方法可以包括启用写时钟数据恢复（WCDR）操作模式。 该方法还可以包括在WCDR操作模式和存储器件的另一操作模式期间将WCDR数据从处理单元发送到存储器件。 基于WCDR数据中的相移，可以调整数据总线上的信号与写入时钟信号之间的相位差。 此外，该方法可以包括基于数据总线上的信号与写入时钟信号之间调整的相位差在数据总线上传送信号。

    Write data mask method and system
    9.
    发明申请
    Write data mask method and system 有权
    写数据掩码的方法和系统

    公开(公告)号：US20080052474A1

    公开(公告)日：2008-02-28

    申请号：US11509143

    申请日：2006-08-23

    Applicant: Xiaoling Xu ,  Warren F. Kruger

    Inventor： Xiaoling Xu ,  Warren F. Kruger

    IPC: G06F13/00

    CPC classification number: G11C7/1006 ,  G11C7/1078 ,  G11C7/1096

    Abstract: In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface.

    Abstract translation: 在各种实施例中，通过在接口的地址线上发送数据掩码来消除专用掩码引脚。 存储器控制器从存储器客户端接收对存储器写入操作的请求，并根据客户端发送的写入数据掩码确定写入数据的粒度。 如本文所使用的，粒度表示所接收的写数据掩码的每个位适用的写数据量。 在一个实施例中，存储器控制器基于写入数据的粒度生成特定的写入命令和特定的写入数据掩码。 所生成的写入命令通常是可用的多个写入命令中最有效的，但实施例不限于此。 写命令在接口的命令行上传输，写数据掩码在接口的地址线上传输。

    ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY
    10.
    发明申请
    ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY 审中-公开
    阵列基板和液晶显示

    公开(公告)号：US20130141685A1

    公开(公告)日：2013-06-06

    申请号：US13805476

    申请日：2012-12-04

    Applicant: Xiaoling Xu ,  Jaegeon You

    Inventor： Xiaoling Xu ,  Jaegeon You

    IPC: G02F1/1343

    CPC classification number: G02F1/134336 ,  G02F1/133784 ,  G02F2001/134318 ,  G02F2001/134345

    Abstract: Another embodiment of the present invention provides an array substrate and a liquid crystal display. The array substrate comprises a plurality of gate lines and a plurality of data lines, and the gate lines and the data lines intersect each other to define a plurality of sub-pixel regions; each sub-pixel region comprises a first transparent electrode, a second transparent electrode and a thin film transistor (TFT), and in the sub-pixel region, a first edge of the second transparent electrode away from the TFT and along the direction of the gate lines is parallel to a second edge of a gate line for an adjacent sub-pixel region, and the second edges is the edge, closest to the first edge, of the gate line for the adjacent sub-pixel region.

    Abstract translation: 本发明的另一实施例提供阵列基板和液晶显示器。 阵列基板包括多个栅极线和多个数据线，并且栅极线和数据线彼此相交以限定多个子像素区域; 每个子像素区域包括第一透明电极，第二透明电极和薄膜晶体管（TFT），并且在子像素区域中，第二透明电极的第一边缘远离TFT并且沿着 栅极线与相邻子像素区域的栅极线的第二边缘平行，并且第二边缘是相邻子像素区域的栅极线的最靠近第一边缘的边缘。

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