公开(公告)号：US09628082B1

公开(公告)日：2017-04-18

申请号：US14321577

申请日：2014-07-01

Applicant: Xilinx, Inc.

Inventor： David S. Smith ,  Xiaobao Wang ,  Arvind R. Bomdica ,  Balakrishna Jayadev

IPC: H03K17/16 ,  H03K19/177 ,  H03K3/01

CPC classification number: H03K19/177 ,  H03K3/01 ,  H03K19/018585

Abstract: An apparatus includes a plurality of adjustable driver circuits having output nodes coupled to a signal line. Each adjustable driver circuit is configured to drive the signal line with a portion of a total drive strength indicated by a value of a binary control signal. The apparatus also includes a delay circuit configured to delay the binary control signal provided to each adjustable driver circuit by a respective time period unique to the adjustable driver circuit.

公开(公告)号：US10659215B1

公开(公告)日：2020-05-19

申请号：US16135653

申请日：2018-09-19

Applicant: Xilinx, Inc.

Inventor： Xiaobao Wang ,  Arvind R. Bomdica ,  Balakrishna Jayadev ,  Richard W. Swanson

IPC: G11C7/00 ,  G11C11/00 ,  H04L7/00 ,  G11C7/22 ,  H03L7/081 ,  G11C7/10 ,  G11C29/50

Abstract: Methods and apparatus relate to a 1-to-2 memory interface deserializer circuit that, in a training mode, independently positions even and odd strobes in respective even and odd data windows. In an illustrative example, the deserializer circuit may receive a data signal that encodes even and odd data streams on the rising (even) and falling (odd) edges of a strobe clock signal. During a training mode, the deserializer circuit may independently determine, for example, an optimal temporal delay for each of the even strobe and the odd strobe. Adjustable delay lines dedicated to each of the even and odd strobe signals may simultaneously detect valid data window edges to permit determination of a desired delay to optimally position the strobe signals. Various embodiments may advantageously reduce jitter associated with asymmetric strobe and/or data signals to achieve a predetermined specification (e.g., timing margins) within the corresponding data windows.

公开(公告)号：US11196418B1

公开(公告)日：2021-12-07

申请号：US16842610

申请日：2020-04-07

Applicant: Xilinx, Inc.

Inventor： Samudyatha Suryanarayana ,  Vinit Shah ,  David S. Smith ,  Andrew Tabalujan ,  Arvind R. Bomdica

IPC: H03K19/00 ,  G11C11/4093 ,  H04L25/02

Abstract: Apparatus and associated methods relate to an I/O bank impedance calibration circuit having (a) a replica master resistor coupled to an external precision resistor, and (b) a control circuit configured to calibrate an output impedance of the master resistor to generate a calibrated code to control a replica slave resistor in each bank. In an illustrative example, a signal applied to the replica master resistor may be compared against a programmable reference signal. The control circuit may generate the calibrated code, in response to the comparison result, to calibrate the output impedance of the replica master resistor. By implementing the replica master resistor and the replica slave resistor, impedances of a large number of IOs or banks may be calibrated by the impedance calibration circuit using a single one reference pin.

公开(公告)号：US09500700B1

公开(公告)日：2016-11-22

申请号：US14081461

申请日：2013-11-15

Applicant: Xilinx, Inc.

Inventor： Xiaobao Wang ,  Burton M. Leary ,  Amitava Majumdar ,  Arvind R. Bomdica

IPC: G01R31/02 ,  G01R31/28

CPC classification number: G01R31/2851 ,  G01R31/31715 ,  G01R31/31716

Abstract: An integrated circuit enabling the communication of data is described. The integrated circuit comprises an input/output port; a plurality of data converter circuits; and programmable interconnect circuits coupled between the input/output port and the plurality of data converter circuits, the programmable interconnect circuits enabling a connection of the plurality of data converter circuits to the input/output port of the integrated circuit. A method of enabling the communication of data in an integrated circuit is also described.

Abstract translation: 描述了能够进行数据通信的集成电路。 集成电路包括输入/​​输出端口; 多个数据转换器电路; 以及耦合在所述输入/输出端口和所述多个数据转换器电路之间的可编程互连电路，所述可编程互连电路使得所述多个数据转换器电路能够连接到所述集成电路的输入/输出端口。 还描述了能够进行集成电路中的数据通信的方法。

公开(公告)号：US09054645B1

公开(公告)日：2015-06-09

申请号：US14081832

申请日：2013-11-15

Applicant: Xilinx, Inc.

Inventor： Xiaobao Wang ,  Arvind R. Bomdica ,  Vipul D. Badoni

IPC: H03G3/30 ,  H03K19/173 ,  H03F1/02 ,  H03F3/45

CPC classification number: H03F1/0261 ,  H03F3/45197 ,  H03F3/45475 ,  H03F3/45744 ,  H03F2203/45488 ,  H03F2203/45492

Abstract: A programmable receiver implemented in an integrated circuit device is described. The programmable receiver comprises a pre-amplifier circuit coupled to receive an input signal, the pre-amplifier circuit having a programmable current source; and an amplifier circuit coupled to receive an output of the pre-amplifier circuit; wherein the programmable current source is coupled to receive a control signal to enable the receiver to be switched between a high performance mode and a low performance mode. A method of implementing a programmable receiver in an integrated circuit is also described.

Abstract translation: 描述了在集成电路器件中实现的可编程接收器。 所述可编程接收器包括耦合以接收输入信号的前置放大器电路，所述前置放大器电路具有可编程电流源; 以及放大器电路，其耦合以接收所述前置放大器电路的输出; 其中所述可编程电流源被耦合以接收控制信号，以使所述接收器能够在高性能模式和低性能模式之间切换。 还描述了在集成电路中实现可编程接收器的方法。