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    Testing of bonded wafers and structures for testing bonded wafers
    1.
    发明授权
    Testing of bonded wafers and structures for testing bonded wafers 有权

    公开(公告)号：US11119146B1

    公开(公告)日：2021-09-14

    申请号：US16997630

    申请日：2020-08-19

    Applicant: XILINX, INC.

    Inventor： Nui Chong ,  Yan Wang ,  Hui-Wen Lin

    IPC: G01R31/28 ,  H01L21/66

    Abstract: Examples described herein generally relate to testing of bonded wafers and structures implemented for such testing. In an example method, power is applied to a first pad on a stack of bonded wafers. A wafer of the stack includes a process control monitor (PCM) region that includes structure regions. Each structure region is a device under test region, dummy region, and/or chain interconnect region (CIR). The stack includes a serpentine chain test structure (SCTS) electrically connected between first and second metal features in the wafer in first and second CIRs, respectively, in the PCM region. The SCTS includes segments, one or more of which are disposed between neighboring structure regions in the PCM region that are not the first and second CIRs. A signal is detected from a second pad on the stack. The first and second pads are electrically connected to the first and second metal features, respectively.

    Warpage reduction
    2.
    发明授权
    Warpage reduction 有权

    公开(公告)号：US11164749B1

    公开(公告)日：2021-11-02

    申请号：US16571766

    申请日：2019-09-16

    Applicant: XILINX, INC.

    Inventor： Nui Chong ,  Hui-Wen Lin

    IPC: H01L21/302 ,  H01L23/498 ,  H01L21/67 ,  H01L23/00 ,  H01L29/78

    Abstract: Examples described herein provide a method for reducing warpage when stacking semiconductor substrates. In an example, a first substrate is bonded with a second substrate to form a stack. The first substrate comprises a first semiconductor substrate, and the second substrate comprises a second semiconductor substrate. The second semiconductor substrate is thinned, and a first trench is etched into a backside of the thinned second semiconductor substrate. A first stressed material is deposited into the first trench.

    IC die with dummy structures
    3.
    发明授权
    IC die with dummy structures 有权

    公开(公告)号：US11114344B1

    公开(公告)日：2021-09-07

    申请号：US16805398

    申请日：2020-02-28

    Applicant: XILINX, INC.

    Inventor： Hui-Wen Lin ,  Nui Chong ,  Myongseob Kim ,  Henley Liu ,  Ping-Chin Yeh ,  Cheang-whang Chang

    IPC: H01L21/82 ,  H01L23/50 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3105

    Abstract: Integrated circuit (IC) dies and method for manufacturing the same are described herein that mitigate pattern loading effects during manufacture. In one example, the IC includes a die body having a first circuit block separated from an adjacent second circuit block by a buffer zone. The first and second circuit blocks have first and second transistors that are at least partially fabricated from a gate metal layer and disposed immediately adjacent the buffer zone. A dummy structure is formed in the buffer zone and is also at least partially fabricated from the gate metal layer. An amount of gate metal layer material in the dummy structure is selected to mitigate differences in the amount of gate metal layer material in regions of first and second circuit blocks that neighbor each other across the buffer zone.

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