公开(公告)号：US09584145B1

公开(公告)日：2017-02-28

申请号：US15133798

申请日：2016-04-20

申请人： Xilinx, Inc.

发明人： Jaewook Shin ,  Hiva Hedayati

IPC分类号： H03M1/06 ,  H03M1/12 ,  H03M1/00

CPC分类号： H03M1/1028 ,  H03M1/00 ,  H03M1/0624 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1225

摘要： A circuit for compensating for mismatch in a plurality of channels of a time-interleaved analog-to-digital converter is described. The circuit comprises an analog-to-digital converter circuit of a first channel of the plurality of channels configured to receive an analog input signal and to generate a digital value associated with the analog input signal; an arithmetic circuit configured to receive the digital value generated at the output of the analog-to-digital converter; a memory element configured to receive an output of the arithmetic circuit; and an accumulator circuit coupled to the memory element, wherein the accumulator generates an average value that is provided to the arithmetic circuit to modify the digital value generated at the output of the analog-to-digital converter while receiving the analog input signal.

摘要翻译： 描述了用于补偿时间交织的模数转换器的多个通道中的失配的电路。 该电路包括被配置为接收模拟输入信号并产生与模拟输入信号相关联的数字值的多个通道中的第一通道的模拟 - 数字转换器电路; 算术电路，被配置为接收在所述模数转换器的输出处产生的数字值; 存储元件，被配置为接收所述运算电路的输出; 以及耦合到所述存储器元件的累加器电路，其中所述累加器产生提供给所述运算电路的平均值，以在接收所述模拟输入信号的同时修改在所述模拟 - 数字转换器的输出处产生的数字值。

公开(公告)号：US20210152180A1

公开(公告)日：2021-05-20

申请号：US16688130

申请日：2019-11-19

申请人： Xilinx, Inc.

发明人： Jaewook Shin ,  Parag Upadhyaya ,  Shaojun MA

IPC分类号： H03L7/24 ,  H03K3/03 ,  H03L7/099 ,  H03L7/083 ,  H03B5/12 ,  H04L7/033 ,  G06F1/08

摘要： A quadrature clock generator is disclosed. The quadrature clock generator may include a first injection-locked oscillator, a phase interpolator, and a second injection-locked oscillator. The first injection-locked oscillator may generate a first plurality clock signals from a first reference clock signal. The phase interpolator may generate a second reference clock signal from the first plurality of clock signals, and the second injection-locked oscillator may generate a second plurality of clock signals from the second reference clock signal. A first quadrature clock signal may be selected from the first plurality of clock signals and a second quadrature clock signal may be selected from the second plurality of reference clock signals.

公开(公告)号：US11108401B2

公开(公告)日：2021-08-31

申请号：US16688130

申请日：2019-11-19

申请人： Xilinx, Inc.

发明人： Jaewook Shin ,  Parag Upadhyaya ,  Shaojun Ma

IPC分类号： H03L7/24 ,  H03K3/03 ,  H03L7/099 ,  G06F1/08 ,  H03B5/12 ,  H04L7/033 ,  H03L7/083 ,  H04L27/00 ,  H03F3/24 ,  H03F3/21

摘要： A quadrature clock generator is disclosed. The quadrature clock generator may include a first injection-locked oscillator, a phase interpolator, and a second injection-locked oscillator. The first injection-locked oscillator may generate a first plurality clock signals from a first reference clock signal. The phase interpolator may generate a second reference clock signal from the first plurality of clock signals, and the second injection-locked oscillator may generate a second plurality of clock signals from the second reference clock signal. A first quadrature clock signal may be selected from the first plurality of clock signals and a second quadrature clock signal may be selected from the second plurality of reference clock signals.

公开(公告)号：US09503115B1

公开(公告)日：2016-11-22

申请号：US15048720

申请日：2016-02-19

申请人： Xilinx, Inc.

发明人： Jaewook Shin ,  Hiva Hedayati

IPC分类号： H03M1/50 ,  H03M1/12 ,  H03M1/08 ,  H03M1/00

CPC分类号： H03M1/1215 ,  H03M1/0836

摘要： A circuit for implementing a time-interleaved analog-to-digital converter is described. The circuit comprises a sampling clock generator configured to receive a reference clock signal having a first frequency. The sampling clock generator has a first stage sampling clock generator configured to generate a first plurality of clock signals based upon the reference clock signal and having a second frequency, and a second stage sampling clock generator configured to generate, for each clock signal of the first plurality of clock signals, a second plurality of clock signals having a third frequency; a first stage having a plurality of switches configured to receive an analog input signal, wherein each switch of the plurality of switches is controlled by a corresponding clock signal of the first plurality of clock signals; and a second stage having a plurality of analog-to-digital converter banks, each analog-to-digital converter bank having a plurality of analog-to-digital converters and configured to receive the analog input signal by way of a corresponding switch of the plurality of switches.

摘要翻译： 描述了用于实现时间交织的模数转换器的电路。 电路包括被配置为接收具有第一频率的参考时钟信号的采样时钟发生器。 采样时钟发生器具有第一级采样时钟发生器，其被配置为基于参考时钟信号产生第一多个时钟信号并具有第二频率，以及第二级采样时钟发生器，被配置为针对第一级采样时钟信号的每个时钟信号产生 多个时钟信号，具有第三频率的第二多个时钟信号; 第一级具有被配置为接收模拟输入信号的多个开关，其中所述多个开关中的每个开关由所述第一多个时钟信号的相应时钟信号控制; 以及具有多个模数转换器组的第二级，每个模数转换器组具有多个模数转换器，并被配置为通过相应的开关转换器接收模拟输入信号 多个开关。