公开(公告)号：US20170033774A1

公开(公告)日：2017-02-02

申请号：US14814401

申请日：2015-07-30

Applicant: Xilinx, Inc.

Inventor： Hiva Hedayati ,  Yohan Frans

IPC: H03K3/017

CPC classification number: H03K3/017 ,  G06F1/04 ,  H03K5/1565

Abstract: Techniques for correcting clock distortion. The techniques include use of circuitry for detecting and correcting duty cycle distortion and quadrature clock phase distortion. For phase detection, detection circuitry is made simpler and more accurate through the use of a sampling operation in which device mismatch within detection circuitry is accounted for by sampling charge associated with an ideal clock signal across sampling capacitors. When phase detection is performed with the detection circuitry, the stored charge compensates for the device mismatch, improving the accuracy of the detection circuit. The sampling operation is used for duty cycle distortion detection as well. Specifically, a common mode voltage is applied to sampling capacitors, which effectively zeroes the voltage differential between the sampling capacitors, compensating for offset that might exist due to operation of other components of the detection circuit. A digital value is used by a feedback algorithm to correct the clock distortion.

Abstract translation: 校正时钟失真的技术。 这些技术包括使用用于检测和校正占空比失真和正交时钟相位失真的电路。 对于相位检测，通过使用采样操作使得检测电路变得更简单和更准确，其中检测电路中的器件失配通过采样电容器两端的理想时钟信号的采样电荷来考虑。 当用检测电路执行相位检测时，存储的电荷补偿器件不匹配，提高检测电路的精度。 采样操作也用于占空比失真检测。 具体地说，共模电压被施加到采样电容器，这样使得采样电容器之间的电压差有效地被归零，从而补偿由于检测电路的其它部件的操作而可能存在的偏移。 反馈算法使用数字值来校正时钟失真。

公开(公告)号：US09503115B1

公开(公告)日：2016-11-22

申请号：US15048720

申请日：2016-02-19

Applicant: Xilinx, Inc.

Inventor： Jaewook Shin ,  Hiva Hedayati

IPC: H03M1/50 ,  H03M1/12 ,  H03M1/08 ,  H03M1/00

CPC classification number: H03M1/1215 ,  H03M1/0836

Abstract: A circuit for implementing a time-interleaved analog-to-digital converter is described. The circuit comprises a sampling clock generator configured to receive a reference clock signal having a first frequency. The sampling clock generator has a first stage sampling clock generator configured to generate a first plurality of clock signals based upon the reference clock signal and having a second frequency, and a second stage sampling clock generator configured to generate, for each clock signal of the first plurality of clock signals, a second plurality of clock signals having a third frequency; a first stage having a plurality of switches configured to receive an analog input signal, wherein each switch of the plurality of switches is controlled by a corresponding clock signal of the first plurality of clock signals; and a second stage having a plurality of analog-to-digital converter banks, each analog-to-digital converter bank having a plurality of analog-to-digital converters and configured to receive the analog input signal by way of a corresponding switch of the plurality of switches.

Abstract translation: 描述了用于实现时间交织的模数转换器的电路。 电路包括被配置为接收具有第一频率的参考时钟信号的采样时钟发生器。 采样时钟发生器具有第一级采样时钟发生器，其被配置为基于参考时钟信号产生第一多个时钟信号并具有第二频率，以及第二级采样时钟发生器，被配置为针对第一级采样时钟信号的每个时钟信号产生 多个时钟信号，具有第三频率的第二多个时钟信号; 第一级具有被配置为接收模拟输入信号的多个开关，其中所述多个开关中的每个开关由所述第一多个时钟信号的相应时钟信号控制; 以及具有多个模数转换器组的第二级，每个模数转换器组具有多个模数转换器，并被配置为通过相应的开关转换器接收模拟输入信号 多个开关。

公开(公告)号：US09602082B2

公开(公告)日：2017-03-21

申请号：US14814401

申请日：2015-07-30

Applicant: Xilinx, Inc.

Inventor： Hiva Hedayati ,  Yohan Frans

IPC: H03K3/017

CPC classification number: H03K3/017 ,  G06F1/04 ,  H03K5/1565

Abstract: Techniques for correcting clock distortion. The techniques include use of circuitry for detecting and correcting duty cycle distortion and quadrature clock phase distortion. For phase detection, detection circuitry is made simpler and more accurate through the use of a sampling operation in which device mismatch within detection circuitry is accounted for by sampling charge associated with an ideal clock signal across sampling capacitors. When phase detection is performed with the detection circuitry, the stored charge compensates for the device mismatch, improving the accuracy of the detection circuit. The sampling operation is used for duty cycle distortion detection as well. Specifically, a common mode voltage is applied to sampling capacitors, which effectively zeroes the voltage differential between the sampling capacitors, compensating for offset that might exist due to operation of other components of the detection circuit. A digital value is used by a feedback algorithm to correct the clock distortion.

公开(公告)号：US09490832B1

公开(公告)日：2016-11-08

申请号：US14942601

申请日：2015-11-16

Applicant: Xilinx, Inc.

Inventor： Lei Zhou ,  Hiva Hedayati

IPC: H03M1/06 ,  H03M1/08 ,  H03M1/46

CPC classification number: H03M1/0872 ,  H03K3/35613 ,  H03M1/468

Abstract: An analog-to-digital converter circuit is described. The analog-to-digital converter circuit comprises an amplifier circuit configured to receive a differential analog input signal at a first amplifier input associated with a first amplifier current path and a second amplifier input associated with a second amplifier current path, and to generate an amplified differential analog input signal at a first amplifier output associated with the first amplifier current path and a second amplifier output associated with the second amplifier current path; a first capacitor coupled between the first amplifier input and the second amplifier output; a second capacitor coupled between the second amplifier input and the first amplifier output; and a latch circuit having a first latch input coupled to the first amplifier output and a second latch input coupled to the second amplifier output, wherein the latch circuit is configured to generate a differential digital output signal, based upon the amplified differential analog input signal, at a first latch output and a second latch output.

Abstract translation: 描述了一种模拟 - 数字转换器电路。 模数转换器电路包括放大器电路，其被配置为在与第一放大器电流路径相关联的第一放大器输入端和与第二放大器电流路径相关联的第二放大器输入端接收差分模拟输入信号，并且产生放大 与第一放大器电流路径相关联的第一放大器输出处的差分模拟输入信号和与第二放大器电流路径相关联的第二放大器输出; 耦合在第一放大器输入和第二放大器输出之间的第一电容器; 耦合在第二放大器输入和第一放大器输出之间的第二电容器; 以及锁存电路，其具有耦合到第一放大器输出的第一锁存器输入和耦合到第二放大器输出的第二锁存器输入，其中锁存电路被配置为基于放大的差分模拟输入信号产生差分数字输出信号， 在第一锁存器输出端和第二锁存器输出端。

公开(公告)号：US09584145B1

公开(公告)日：2017-02-28

申请号：US15133798

申请日：2016-04-20

Applicant: Xilinx, Inc.

Inventor： Jaewook Shin ,  Hiva Hedayati

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/00

CPC classification number: H03M1/1028 ,  H03M1/00 ,  H03M1/0624 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1225

Abstract: A circuit for compensating for mismatch in a plurality of channels of a time-interleaved analog-to-digital converter is described. The circuit comprises an analog-to-digital converter circuit of a first channel of the plurality of channels configured to receive an analog input signal and to generate a digital value associated with the analog input signal; an arithmetic circuit configured to receive the digital value generated at the output of the analog-to-digital converter; a memory element configured to receive an output of the arithmetic circuit; and an accumulator circuit coupled to the memory element, wherein the accumulator generates an average value that is provided to the arithmetic circuit to modify the digital value generated at the output of the analog-to-digital converter while receiving the analog input signal.

Abstract translation: 描述了用于补偿时间交织的模数转换器的多个通道中的失配的电路。 该电路包括被配置为接收模拟输入信号并产生与模拟输入信号相关联的数字值的多个通道中的第一通道的模拟 - 数字转换器电路; 算术电路，被配置为接收在所述模数转换器的输出处产生的数字值; 存储元件，被配置为接收所述运算电路的输出; 以及耦合到所述存储器元件的累加器电路，其中所述累加器产生提供给所述运算电路的平均值，以在接收所述模拟输入信号的同时修改在所述模拟 - 数字转换器的输出处产生的数字值。

公开(公告)号：US09584144B1

公开(公告)日：2017-02-28

申请号：US15135073

申请日：2016-04-21

Applicant: Xilinx, Inc.

Inventor： Lei Zhou ,  Hiva Hedayati

IPC: H03M1/38 ,  H03M1/00 ,  H03K5/15 ,  H03K19/00 ,  H03M1/46 ,  H03M1/12

CPC classification number: H03K19/0013 ,  H03K5/15026 ,  H03M1/1215 ,  H03M1/46 ,  H03M1/462

Abstract: A clock generator includes: a first input to receive a global clock signal; a second input to receive a completion signal; a third input to receive differential outputs in a conversion cycle from a comparator; and a logic circuit configured to generate a control clock signal based at least in part on the global clock signal and the differential outputs, and to provide the control clock signal to the comparator for a next conversion cycle; and wherein the logic circuit is also configured to disable the control clock signal in response to the completion signal indicating a completion of required conversion cycles in a conversion phase.

Abstract translation: 时钟发生器包括：接收全局时钟信号的第一输入; 用于接收完成信号的第二输入; 第三输入端，用于从比较器接收转换周期中的差分输出; 以及逻辑电路，被配置为至少部分地基于所述全局时钟信号和所述差分输出来产生控制时钟信号，并且将所述控制时钟信号提供给所述比较器用于下一个转换周期; 并且其中所述逻辑电路还被配置为响应于指示在转换阶段中所需的转换周期的完成的所述完成信号来禁用所述控制时钟信号。