公开(公告)号：US11169945B1

公开(公告)日：2021-11-09

申请号：US16675997

申请日：2019-11-06

Applicant: Xilinx, Inc.

Inventor： Danny Tsung-Heng Wu ,  Roger D. Flateau, Jr.

IPC: G06F13/40 ,  G06F9/54 ,  G06F13/42 ,  G06F9/4401

Abstract: A device includes a processor, an SBI, and a plurality of interfaces. The processor is configured to manage operations of the device. The SBI is coupled to the processor. The plurality of interfaces is associated with the SBI. The interfaces of the plurality of interfaces have different interface protocol from one another. The SBI is configured by the processor and the configuration of the SBI activates one interface of the plurality of interfaces at any given time. The active interface that is selected from the plurality of interfaces and a host have a same interface protocol. The active interface is configured to receive host data from the host. The SBI is configured to generate a flag for the processor in response to the active interface receiving the host data. The SBI is configured to transmit device data to the host.

公开(公告)号：US10861578B1

公开(公告)日：2020-12-08

申请号：US16718535

申请日：2019-12-18

Applicant: Xilinx, Inc.

Inventor： Roger D. Flateau, Jr. ,  Tomai Knopp

IPC: G11C29/44 ,  G11C29/00 ,  G11C29/24 ,  G11C29/14 ,  G11C29/04

Abstract: A device includes a plurality of memory components with redundant columns associated therewith, a sub-block controller, and a volatile memory. The sub-block controller generates a repair vector, during manufacture testing mode. The repair vector is associated with the plurality of memory components and is generated responsive to detecting a defect within a column of the plurality of memory components. No repair vector is generated responsive to detecting no defect within a column of the plurality of memory components. The volatile memory receives and stores the repair vector in a nonvolatile memory component, during the manufacture testing mode. The volatile memory receives the repair vector from the nonvolatile memory component if the repair vector was generated during the manufacture testing mode, at startup mode, and provides it to the sub-block controller. The sub-block controller loads a repair data into the plurality of memory components based on the repair vector.

公开(公告)号：US09230112B1

公开(公告)日：2016-01-05

申请号：US13775151

申请日：2013-02-23

Applicant: Xilinx, Inc.

Inventor： Edward S. Peterson ,  Roger D. Flateau, Jr. ,  James D. Wesselkamper ,  Steven E. McNeil ,  Jason J. Moore ,  Lester S. Sanders ,  Lawrence C. Hung ,  Yatharth K. Kochar

IPC: G06F9/00 ,  G06F15/177 ,  G06F21/57 ,  G06F9/44 ,  G06F21/76

CPC classification number: G06F21/575 ,  G06F9/4401 ,  G06F9/4406 ,  G06F9/4416 ,  G06F21/76

Abstract: A system generally relating to an SoC, which may be a field programmable SoC (“FPSoC”), is disclosed. In this SoC, dedicated hardware includes a processing unit, a first internal memory, a second internal memory, an authentication engine, and a decryption engine. A storage device is coupled to the SoC. The storage device has access to a boot image. The first internal memory has boot code stored therein. The boot code is for a secure boot of the SoC. The boot code is configured to cause the processing unit to control the secure boot.

Abstract translation: 通常涉及可能是现场可编程SoC（“FPSoC”）的SoC的系统被公开。 在该SoC中，专用硬件包括处理单元，第一内部存储器，第二内部存储器，认证引擎和解密引擎。 存储设备耦合到SoC。 存储设备可以访问引导映像。 第一内部存储器具有存储在其中的引导代码。 引导代码用于安全引导SoC。 引导代码被配置为使处理单元控制安全启动。

公开(公告)号：US11199582B2

公开(公告)日：2021-12-14

申请号：US16841564

申请日：2020-04-06

Applicant: XILINX, INC.

Inventor： Roger D. Flateau, Jr. ,  Srinu Sunkara

IPC: G01R31/3177 ,  G06F9/30 ,  G01R31/317 ,  G08G1/0968

Abstract: An example integrated circuit (IC) die in a multi-die IC package, the multi-die IC package having a test access port (TAP) comprising a test data input (TDI), test data output (TDO), test clock (TCK), and test mode select (TMS), is described. The IC die includes a Joint Test Action Group (JTAG) controller having a JTAG interface that includes a TDI, a TDO, a TCK, and a TMS, a first output coupled to first routing in the multi-die IC package, a first input coupled to the first routing or to second routing in the multi-die IC package, a master return path coupled to the first input, and a wrapper circuit configured to couple the TDI of the TAP to the TDI of the JTAG controller, and selectively couple, in response to a first control signal, the TDO of the TAP to either the master return path or the TDO of the JTAG controller.

公开(公告)号：US09165143B1

公开(公告)日：2015-10-20

申请号：US13833177

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Lester S. Sanders ,  Yatharth K. Kochar ,  Steven E. McNeil ,  Jason J. Moore ,  Roger D. Flateau, Jr. ,  Lawrence C. Hung

IPC: G06F11/30 ,  G06F12/14 ,  G06F21/57

CPC classification number: G06F21/575 ,  G06F21/572 ,  G06F21/76

Abstract: A method relating generally to loading a boot image is disclosed. In such a method, a header of a boot image file is read by boot code executed by a system-on-chip. It is determined whether the header read has an authentication certificate. If the header has the authentication certificate, authenticity of the header is verified with the first authentication certificate. It is determined whether the header is encrypted. If the header is encrypted, the header is decrypted.

Abstract translation: 公开了一般涉及加载引导图像的方法。 在这种方法中，通过由片上系统执行的引导代码来读取引导映像文件的标题。 确定头读取是否具有认证证书。 如果标头具有认证证书，则使用第一认证证书验证报头的真实性。 确定头部是否被加密。 如果标题被加密，则头部被解密。

公开(公告)号：US11675006B2

公开(公告)日：2023-06-13

申请号：US17644067

申请日：2021-12-13

Applicant: XILINX, INC.

Inventor： Roger D. Flateau, Jr. ,  Srinu Sunkara

IPC: G01R31/3177 ,  G01R31/317 ,  G06F9/30 ,  G08G1/0968

CPC classification number: G01R31/3177 ,  G01R31/31701 ,  G01R31/31712 ,  G01R31/31727 ,  G06F9/30145 ,  G08G1/096805 ,  G08G1/096811 ,  G08G1/096816 ,  G08G1/096822

Abstract: An example integrated circuit (IC) die in a multi-die IC package, the multi-die IC package having a test access port (TAP) comprising a test data input (TDI), test data output (TDO), test clock (TCK), and test mode select (TMS), is described. The IC die includes a Joint Test Action Group (JTAG) controller having a JTAG interface that includes a TDI, a TDO, a TCK, and a TMS, a first output coupled to first routing in the multi-die IC package, a first input coupled to the first routing or to second routing in the multi-die IC package, a master return path coupled to the first input, and a wrapper circuit configured to couple the TDI of the TAP to the TDI of the JTAG controller, and selectively couple, in response to a first control signal, the TDO of the TAP to either the master return path or the TDO.

公开(公告)号：US11422879B1

公开(公告)日：2022-08-23

申请号：US17206075

申请日：2021-03-18

Applicant: XILINX, INC.

Inventor： Andrew Thomas Novotny ,  Roger D. Flateau, Jr.

IPC: G06F11/07 ,  G06F13/20

Abstract: Embodiments herein describe error interceptors disposed along a bus that communicatively couples first and second circuits for redirecting in-band errors. That is, the error interceptors can block (or mask) in-band errors so they are not forwarded along the bus. Further, the error interceptors can redirect those errors such that they are converted into out-of-band errors. Moreover, the user can select which error interceptors to activate (e.g., block and redirect the errors) and which to deactivate (e.g., permit the in-band errors to pass). In this manner, the user can control which circuits receive in-band errors and which do not based on whether those circuits can handle the in-band errors.

公开(公告)号：US11379580B1

公开(公告)日：2022-07-05

申请号：US16819864

申请日：2020-03-16

Applicant: Xilinx, Inc.

Inventor： James D. Wesselkamper ,  Edward S. Peterson ,  Jason J. Moore ,  Steven E. McNeil ,  Roger D. Flateau, Jr. ,  Danny Tsung-Heng Wu ,  Boon Y. Ang

IPC: G06F21/55 ,  G06F21/72 ,  H04L9/32 ,  G11C29/00 ,  G11C29/08

Abstract: An array of non-volatile memory cells includes rows and columns. A volatile storage circuit provides addressable units of storage. A control circuit reads first type data and second type data from one or more of the rows and multiple ones of the columns of the array of non-volatile memory cells. The control circuit stores the first type data and second type data read from each row in one or more addressable units of storage of the volatile storage. A security circuit reads first data from the one or more of the addressable units of the volatile storage and selects from the first data, the second type data that includes one or more bits of each of the one or more of the addressable units. The security circuit performs an integrity check on the selected second type data, and generates an alert signal that indicates a security violation in response to failure of the integrity check.

公开(公告)号：US09130566B1

公开(公告)日：2015-09-08

申请号：US14495811

申请日：2014-09-24

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Roger D. Flateau, Jr.

IPC: H03K19/177 ,  H03K19/007

CPC classification number: H03K19/17764 ,  H03K19/007 ,  H03K19/17748

Abstract: A programmable IC is disclosed that includes a programmable logic sub-system, a processing sub-system, and a safety sub-system. The programmable logic circuits in the programmable logic sub-system are configured to form a set of circuits indicated in a set of configuration data. The processing sub-system also executes a software program included in the set of configuration data. The programmable logic sub-system and the processing sub-system are independently powered. In response to a power failure of the processing sub-system and continued power to the programmable logic sub-system, the safety sub-system resets only the processing sub-system. In response to a power failure of the programmable logic sub-system and continued power to the processing sub-system, the safety sub-system resets only the programmable logic sub-system.

Abstract translation: 公开了一种可编程IC，其包括可编程逻辑子系统，处理子系统和安全子系统。 可编程逻辑子系统中的可编程逻辑电路被配置为形成在一组配置数据中指示的一组电路。 处理子系统还执行包括在该组配置数据中的软件程序。 可编程逻辑子系统和处理子系统是独立供电的。 响应于处理子系统的电源故障和对可编程逻辑子系统的持续供电，安全子系统仅复位处理子系统。 响应于可编程逻辑子系统的电源故障和对处理子系统的持续供电，安全子系统仅复位可编程逻辑子系统。