公开(公告)号：US10853308B1

公开(公告)日：2020-12-01

申请号：US16195218

申请日：2018-11-19

Applicant: Xilinx, Inc.

Inventor： Ramesh R. Subramanian ,  Ravinder Sharma ,  Jayaram Pvss ,  Michael Zapke ,  Manjunath Chepuri

IPC: G06F15/167 ,  G06F15/173 ,  G06F13/28

Abstract: A circuit for memory access includes a memory access control circuit. The memory access controller is coupled to a memory and configured to perform data transfers to retrieve data from the memory. The memory access control circuit includes a timing control circuit and a transfer control circuit. The timing control circuit is configured to determine first timing information based on a timing requirement for transmitting a first data stream to a first network; and determine a first fetch time for retrieving the first data stream from the memory based on the first timing information. The transfer control circuit is configured to retrieve the first data stream from the memory based on the first fetch time.

公开(公告)号：US11386034B2

公开(公告)日：2022-07-12

申请号：US17085740

申请日：2020-10-30

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Ravi N. Kurlagunda ,  Min Ma ,  Himanshu Choudhary ,  Manjunath Chepuri ,  Cheng Zhen ,  Pranjal Joshi ,  Sebastian Turullols ,  Amit Kumar ,  Kaustuv Manji ,  Ravinder Sharma ,  Ch Vamshi Krishna

IPC: G06F13/42

Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.

公开(公告)号：US20220138140A1

公开(公告)日：2022-05-05

申请号：US17085740

申请日：2020-10-30

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Ravi N. Kurlagunda ,  Min Ma ,  Himanshu Choudhary ,  Manjunath Chepuri ,  Cheng Zhen ,  Pranjal Joshi ,  Sebastian Turullols ,  Amit Kumar ,  Kaustuv Manji ,  Ravinder Sharma ,  Ch Vamshi Krishna

IPC: G06F13/42

Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.