公开(公告)号：US11029964B1

公开(公告)日：2021-06-08

申请号：US16282216

申请日：2019-02-21

Applicant: Xilinx, Inc.

Inventor： Siddharth Rele ,  Shreegopal S. Agrawal ,  Kaustuv Manji ,  Aditya Chaubal

IPC: G06F9/4401 ,  G06F21/30 ,  G06F15/78

Abstract: Approaches for configuring a system-on-chip (SOC) include generating component images for components of the SOC. A first component image is for a platform management controller, a second component image is for programmable logic, and a third component image is for a processor subsystem. The plurality of component images are assembled into a programmable device image, and the programmable device image is input to the platform management controller. The platform management controller is booted from the first component image, the programmable logic is configured with the second component image by the platform management controller in executing the first component image, and the processor subsystem is configured with the third component image by the platform management controller in executing the first component image.

公开(公告)号：US20230055704A1

公开(公告)日：2023-02-23

申请号：US17408218

申请日：2021-08-20

Applicant: Xilinx, Inc.

Inventor： Sebastian Turullols ,  Kyle Corbett ,  Sudipto Chakraborty ,  Siva Santosh Kumar Pyla ,  Ravinder Sharma ,  Kaustuv Manji ,  Jayaram PVSS ,  Stephen P. Rozum ,  Ch Vamshi Krishna ,  Susheel Puthana

IPC: G06F30/392 ,  G06F30/3953 ,  G06F30/398

Abstract: Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

公开(公告)号：US11720735B2

公开(公告)日：2023-08-08

申请号：US17408218

申请日：2021-08-20

Applicant: Xilinx, Inc.

Inventor： Sebastian Turullols ,  Kyle Corbett ,  Sudipto Chakraborty ,  Siva Santosh Kumar Pyla ,  Ravinder Sharma ,  Kaustuv Manji ,  Jayaram Pvss ,  Stephen P. Rozum ,  Ch Vamshi Krishna ,  Susheel Puthana

IPC: G06F30/392 ,  G06F30/398 ,  G06F30/3953

CPC classification number: G06F30/392 ,  G06F30/398 ,  G06F30/3953

Abstract: Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

公开(公告)号：US11507394B1

公开(公告)日：2022-11-22

申请号：US17408152

申请日：2021-08-20

Applicant: Xilinx, Inc.

Inventor： Siva Santosh Kumar Pyla ,  Ravinder Sharma ,  Gokul Kavungal Nechikott ,  Saifuddin Kaijar ,  Brian S. Martin ,  Suraj Patel ,  Rishabh Gupta ,  Ch Vamshi Krishna ,  Kaustuv Manji

IPC: G06F9/445 ,  G06F9/4401 ,  G06F13/42

Abstract: Changing accelerator card images without rebooting a host system includes receiving, within an integrated circuit (IC) of an accelerator card, an address of a platform image stored in a non-volatile memory of the accelerator card. The address is received over a communication link between the host system and the accelerator card while the communication link is connected. Changing accelerator card images includes detecting, within a register of the IC, that a warm boot enable flag is set and that the communication link with the host system is disconnected. In response to detecting that the warm boot enable flag is set and that the communication link is disconnected, loading of the platform image from the address of the non-volatile memory into the integrated circuit is initiated.

公开(公告)号：US11386034B2

公开(公告)日：2022-07-12

申请号：US17085740

申请日：2020-10-30

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Ravi N. Kurlagunda ,  Min Ma ,  Himanshu Choudhary ,  Manjunath Chepuri ,  Cheng Zhen ,  Pranjal Joshi ,  Sebastian Turullols ,  Amit Kumar ,  Kaustuv Manji ,  Ravinder Sharma ,  Ch Vamshi Krishna

IPC: G06F13/42

Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.

公开(公告)号：US20220138140A1

公开(公告)日：2022-05-05

申请号：US17085740

申请日：2020-10-30

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Ravi N. Kurlagunda ,  Min Ma ,  Himanshu Choudhary ,  Manjunath Chepuri ,  Cheng Zhen ,  Pranjal Joshi ,  Sebastian Turullols ,  Amit Kumar ,  Kaustuv Manji ,  Ravinder Sharma ,  Ch Vamshi Krishna

IPC: G06F13/42

Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.