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    Power and temperature driven clock throttling
    2.
    发明授权
    Power and temperature driven clock throttling 有权

    公开(公告)号：US11709522B1

    公开(公告)日：2023-07-25

    申请号：US17023016

    申请日：2020-09-16

    Applicant: XILINX, INC.

    Inventor： Sebastian Turullols ,  Ravinder Sharma ,  Siva Santosh Kumar Pyla ,  Raj Kumar Rampelli ,  Deboleena Minz Sakalley ,  Nilay Shah

    IPC: G06F1/26 ,  G06F1/08

    CPC classification number: G06F1/08 ,  G06F1/26

    Abstract: Embodiments herein describe techniques for managing power consumption and temperature in an electronic circuits or integrated chips driven by clock signals (collectively referred to as “cards”) by throttling the clock signals on those cards. The cards often allow users to implement customized hardware acceleration functions via Field Programmable Gate Arrays or the like, which can lead to variable workloads on different cards (or regions of individual cards) based on the customized functionality. By throttling the clock signal based on continuously monitored power consumption or temperature, the user is enabled to use the card more aggressively (e.g., based on average rather than worst-case power consumption), and the card automatically throttles operations when power consumption or temperature exceeds operational thresholds.

    Method and apparatus for direct memory access transfers
    3.
    发明授权
    Method and apparatus for direct memory access transfers 有权

    公开(公告)号：US10853308B1

    公开(公告)日：2020-12-01

    申请号：US16195218

    申请日：2018-11-19

    Applicant: Xilinx, Inc.

    Inventor： Ramesh R. Subramanian ,  Ravinder Sharma ,  Jayaram Pvss ,  Michael Zapke ,  Manjunath Chepuri

    IPC: G06F15/167 ,  G06F15/173 ,  G06F13/28

    Abstract: A circuit for memory access includes a memory access control circuit. The memory access controller is coupled to a memory and configured to perform data transfers to retrieve data from the memory. The memory access control circuit includes a timing control circuit and a transfer control circuit. The timing control circuit is configured to determine first timing information based on a timing requirement for transmitting a first data stream to a first network; and determine a first fetch time for retrieving the first data stream from the memory based on the first timing information. The transfer control circuit is configured to retrieve the first data stream from the memory based on the first fetch time.

    Systems and methods for frame buffering and arbitration in a network
    4.
    发明授权
    Systems and methods for frame buffering and arbitration in a network 有权

    公开(公告)号：US10541934B1

    公开(公告)日：2020-01-21

    申请号：US15837400

    申请日：2017-12-11

    Applicant: Xilinx, Inc.

    Inventor： Ramesh R. Subramanian ,  Ravinder Sharma ,  Ashish Banga

    IPC: H04L12/863 ,  H04L12/947

    Abstract: A network device includes a first port, a second port, a third port, and an arbitration circuit. The arbitration circuit is configured to receive a first frame and a second frame. The first frame is received from the first port and to be forwarded to the third port. The second frame is received from the second port and to be forwarded to the third port. The arbitration circuit compares a first priority of the first frame and a second priority of the second frame to generate a first comparison result. In response to the first comparison result, first forwarding data is generated based on the first and second frames. The first forwarding data is sent to an output of the arbitration circuit.

    Adaptive video direct memory access module
    7.
    发明授权
    Adaptive video direct memory access module 有权
    自适应视频直接存储器访问模块

    公开(公告)号：US09558528B2

    公开(公告)日：2017-01-31

    申请号：US14668184

    申请日：2015-03-25

    Applicant: Xilinx, Inc.

    Inventor： Alagar Rengarajan ,  Ravinder Sharma

    IPC: G06F3/00 ,  G06T1/00 ,  G06T1/20 ,  G06F3/06 ,  G06T1/60

    CPC classification number: G06T1/20 ,  G06F3/06 ,  G06F2003/0691 ,  G06F2003/0692 ,  G06T1/60

    Abstract: A method, computing device, and non-transitory computer-readable medium for arbitrating data for channels in a video pipeline. The method includes determining arbitration weights for the channels. The method also includes determining which channels have arbitration weights above a threshold. The method further includes issuing data to the channels with arbitration weights above the threshold. The method also includes decrementing arbitration weights for channels for which data is issued. The method further includes repeating the determining, issuing, and decrementing until no channels have arbitration weights above the threshold.

    Abstract translation: 一种用于对视频流水线中的信道的数据进行仲裁的方法，计算装置和非暂时计算机可读介质。 该方法包括确定信道的仲裁权重。 该方法还包括确定哪些信道具有高于阈值的仲裁权重。 该方法还包括以高于阈值的仲裁权重向信道发布数据。 该方法还包括递减发送数据的信道的仲裁权重。 该方法还包括重复确定，发出和递减，直到没有信道具有高于阈值的仲裁权重。

    Time sensitive networking control circuitry
    10.
    发明授权
    Time sensitive networking control circuitry 有权

    公开(公告)号：US10511455B1

    公开(公告)日：2019-12-17

    申请号：US15707911

    申请日：2017-09-18

    Applicant: Xilinx, Inc.

    Inventor： Ravinder Sharma ,  Ramesh R. Subramanian ,  Ashish Banga

    IPC: G06F9/44 ,  H04L12/18 ,  H04L12/841 ,  H04L29/06 ,  H04L12/851 ,  H04L12/853

    Abstract: A time-sensitive networking system includes gate control circuits configured to control egress of data from multiple queues, respectively. A list execution circuit configures gate states of the plurality of gate control circuits based on a current gate control list that specifies a sequence of operations. Each operation specifies the gate states of the gate control circuits. A cycle timer circuit transmits a timing signal that signals to start a gating cycle by the list execution circuit. A list configuration circuit inputs a new gate control list and establishes the new gate control list as the current gate control list. The list configuration circuit transmits an initial cycle start signal directly to the list execution circuit, bypassing the cycle timer circuit, in response to completion of establishing the new gate control list as the current gate control list.

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