公开(公告)号：US20230055704A1

公开(公告)日：2023-02-23

申请号：US17408218

申请日：2021-08-20

Applicant: Xilinx, Inc.

Inventor： Sebastian Turullols ,  Kyle Corbett ,  Sudipto Chakraborty ,  Siva Santosh Kumar Pyla ,  Ravinder Sharma ,  Kaustuv Manji ,  Jayaram PVSS ,  Stephen P. Rozum ,  Ch Vamshi Krishna ,  Susheel Puthana

IPC: G06F30/392 ,  G06F30/3953 ,  G06F30/398

Abstract: Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.

公开(公告)号：US11709522B1

公开(公告)日：2023-07-25

申请号：US17023016

申请日：2020-09-16

Applicant: XILINX, INC.

Inventor： Sebastian Turullols ,  Ravinder Sharma ,  Siva Santosh Kumar Pyla ,  Raj Kumar Rampelli ,  Deboleena Minz Sakalley ,  Nilay Shah

IPC: G06F1/26 ,  G06F1/08

CPC classification number: G06F1/08 ,  G06F1/26

Abstract: Embodiments herein describe techniques for managing power consumption and temperature in an electronic circuits or integrated chips driven by clock signals (collectively referred to as “cards”) by throttling the clock signals on those cards. The cards often allow users to implement customized hardware acceleration functions via Field Programmable Gate Arrays or the like, which can lead to variable workloads on different cards (or regions of individual cards) based on the customized functionality. By throttling the clock signal based on continuously monitored power consumption or temperature, the user is enabled to use the card more aggressively (e.g., based on average rather than worst-case power consumption), and the card automatically throttles operations when power consumption or temperature exceeds operational thresholds.

公开(公告)号：US11386034B2

公开(公告)日：2022-07-12

申请号：US17085740

申请日：2020-10-30

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Ravi N. Kurlagunda ,  Min Ma ,  Himanshu Choudhary ,  Manjunath Chepuri ,  Cheng Zhen ,  Pranjal Joshi ,  Sebastian Turullols ,  Amit Kumar ,  Kaustuv Manji ,  Ravinder Sharma ,  Ch Vamshi Krishna

IPC: G06F13/42

Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.

公开(公告)号：US20220138140A1

公开(公告)日：2022-05-05

申请号：US17085740

申请日：2020-10-30

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Ravi N. Kurlagunda ,  Min Ma ,  Himanshu Choudhary ,  Manjunath Chepuri ,  Cheng Zhen ,  Pranjal Joshi ,  Sebastian Turullols ,  Amit Kumar ,  Kaustuv Manji ,  Ravinder Sharma ,  Ch Vamshi Krishna

IPC: G06F13/42

Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.

公开(公告)号：US11720735B2

公开(公告)日：2023-08-08

申请号：US17408218

申请日：2021-08-20

Applicant: Xilinx, Inc.

Inventor： Sebastian Turullols ,  Kyle Corbett ,  Sudipto Chakraborty ,  Siva Santosh Kumar Pyla ,  Ravinder Sharma ,  Kaustuv Manji ,  Jayaram Pvss ,  Stephen P. Rozum ,  Ch Vamshi Krishna ,  Susheel Puthana

IPC: G06F30/392 ,  G06F30/398 ,  G06F30/3953

CPC classification number: G06F30/392 ,  G06F30/398 ,  G06F30/3953

Abstract: Using a flat shell for an accelerator card includes reading a flat shell from one or more computer readable storage media using computer hardware, wherein the flat shell is a synthesized, unplaced, and unrouted top-level circuit design specifying platform circuitry. A kernel specifying user circuitry is synthesized using the computer hardware. The kernel is obtained from the one or more computer readable storage media. The synthesized kernel is linked, using the computer hardware, to the flat shell forming a unified circuit design. The unified circuit design is placed and routed, using the computer hardware, to generate a placed and routed circuit design specifying the platform circuitry and the user circuitry for implementation in an integrated circuit.