公开(公告)号：US11159445B1

公开(公告)日：2021-10-26

申请号：US16697155

申请日：2019-11-26

Applicant: Xilinx, Inc.

Inventor： Ramesh R. Subramanian

IPC: H04L29/06 ,  H04L12/865 ,  H04L12/743 ,  H04L12/879 ,  H04L12/875 ,  H04L12/853

Abstract: An integrated circuit (IC) device includes a network device. The network device includes first and second network ports each configured to connect to a network, and an internal endpoint port configured to connect to first endpoint having a first processing unit and second endpoint having a second processing unit. A lookup circuit is configured to provide a first forwarding decision for a first frame to be forwarded to the first endpoint. An endpoint extension circuit is configured to determine a first memory channel based on the first forwarding decision for forwarding the first frame, and forward the first frame to the first endpoint using the determined memory channel.

公开(公告)号：US10853308B1

公开(公告)日：2020-12-01

申请号：US16195218

申请日：2018-11-19

Applicant: Xilinx, Inc.

Inventor： Ramesh R. Subramanian ,  Ravinder Sharma ,  Jayaram Pvss ,  Michael Zapke ,  Manjunath Chepuri

IPC: G06F15/167 ,  G06F15/173 ,  G06F13/28

Abstract: A circuit for memory access includes a memory access control circuit. The memory access controller is coupled to a memory and configured to perform data transfers to retrieve data from the memory. The memory access control circuit includes a timing control circuit and a transfer control circuit. The timing control circuit is configured to determine first timing information based on a timing requirement for transmitting a first data stream to a first network; and determine a first fetch time for retrieving the first data stream from the memory based on the first timing information. The transfer control circuit is configured to retrieve the first data stream from the memory based on the first fetch time.

公开(公告)号：US10541934B1

公开(公告)日：2020-01-21

申请号：US15837400

申请日：2017-12-11

Applicant: Xilinx, Inc.

Inventor： Ramesh R. Subramanian ,  Ravinder Sharma ,  Ashish Banga

IPC: H04L12/863 ,  H04L12/947

Abstract: A network device includes a first port, a second port, a third port, and an arbitration circuit. The arbitration circuit is configured to receive a first frame and a second frame. The first frame is received from the first port and to be forwarded to the third port. The second frame is received from the second port and to be forwarded to the third port. The arbitration circuit compares a first priority of the first frame and a second priority of the second frame to generate a first comparison result. In response to the first comparison result, first forwarding data is generated based on the first and second frames. The first forwarding data is sent to an output of the arbitration circuit.

公开(公告)号：US08943240B1

公开(公告)日：2015-01-27

申请号：US13803920

申请日：2013-03-14

Applicant: Xilinx, Inc.

Inventor： Ramesh R. Subramanian

IPC: G06F3/00 ,  G06F13/00 ,  G06F13/28 ,  G06F5/06

CPC classification number: G06F13/28 ,  G06F3/00 ,  G06F5/065

Abstract: A direct memory access circuit includes a buffer handler configured to store received data within a buffer in a buffer memory coupled to the direct memory access circuit and to generate a descriptor for the buffer. The direct memory access circuit further includes a descriptor handler coupled to the buffer handler. The descriptor handler is configured to determine a descriptor address for the descriptor and to store the descriptor at the determined address within a descriptor memory coupled to the direct memory access circuit.

Abstract translation: 直接存储器访问电路包括缓冲器处理器，其被配置为将连接到直接存储器访问电路的缓冲存储器中的缓冲器内的接收数据存储并生成缓冲器的描述符。 直接存储器访问电路还包括耦合到缓冲器处理器的描述符处理程序。 描述符处理器被配置为确定描述符的描述符地址，并将描述符存储在耦合到直接存储器访问电路的描述符存储器内的所确定的地址处。

公开(公告)号：US11861326B1

公开(公告)日：2024-01-02

申请号：US15092490

申请日：2016-04-06

Applicant: Xilinx, Inc.

Inventor： Santosh Singh ,  Deboleena M. Sakalley ,  Ramesh R. Subramanian ,  Pankaj V. Kumbhare ,  Ravi K. Boddu

IPC: G06F15/16 ,  G06F5/06 ,  G06F3/06 ,  G06F15/173

CPC classification number: G06F5/065 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F15/17331 ,  G06F2205/067

Abstract: An example method of flow control between remote hosts and a target system over a front-end fabric, the target system including a nonvolatile memory (NVM) subsystem coupled to a back end fabric having a different transport than the front-end fabric is described. The method includes receiving commands from the remote hosts at a controller in the target system for the NVM subsystem. The method further includes storing the commands in a first-in-first-out (FIFO) shared among the remote hosts and implemented in memory of the target system. The method further includes updating virtual submission queues for the remote hosts based on the commands stored in the FIFO. The method further includes providing the commands to the NVM subsystem from the FIFO.

公开(公告)号：US10511455B1

公开(公告)日：2019-12-17

申请号：US15707911

申请日：2017-09-18

Applicant: Xilinx, Inc.

Inventor： Ravinder Sharma ,  Ramesh R. Subramanian ,  Ashish Banga

IPC: G06F9/44 ,  H04L12/18 ,  H04L12/841 ,  H04L29/06 ,  H04L12/851 ,  H04L12/853

Abstract: A time-sensitive networking system includes gate control circuits configured to control egress of data from multiple queues, respectively. A list execution circuit configures gate states of the plurality of gate control circuits based on a current gate control list that specifies a sequence of operations. Each operation specifies the gate states of the gate control circuits. A cycle timer circuit transmits a timing signal that signals to start a gating cycle by the list execution circuit. A list configuration circuit inputs a new gate control list and establishes the new gate control list as the current gate control list. The list configuration circuit transmits an initial cycle start signal directly to the list execution circuit, bypassing the cycle timer circuit, in response to completion of establishing the new gate control list as the current gate control list.

公开(公告)号：US10432536B1

公开(公告)日：2019-10-01

申请号：US15837336

申请日：2017-12-11

Applicant: Xilinx, Inc.

Inventor： Ramesh R. Subramanian ,  Ravinder Sharma ,  Ashif Khan Mohammed

IPC: H04L12/813 ,  H04L12/851 ,  H04L12/859 ,  H04L12/927 ,  H04L12/807

Abstract: A network device includes a first port, a second port, and a traffic policer circuit. The traffic policer circuit is configured to provide a frame credit and a credit state associated with the frame credit, receive a start of a first frame of a first stream from the first port, and determine a first estimate frame length of the first frame based on the frame credit and credit state. After the first estimate frame length is generated and prior to an end of the first frame is received, the first frame is metered based on the first estimate frame length to mark the first frame with a first marking. After the end of the first frame is received, the frame credit and credit state are updated based on the first frame. The first frame is forwarded to the second port by policing the first frame based on the first marking.

公开(公告)号：US11388060B1

公开(公告)日：2022-07-12

申请号：US16697144

申请日：2019-11-26

Applicant: Xilinx, Inc.

Inventor： Ramesh R. Subramanian ,  Jayaram Pvss ,  Syed S. Khader

IPC: G06F15/16 ,  H04L41/12 ,  H04L41/0213 ,  G06F13/28 ,  H04L41/0803 ,  H04L69/324

Abstract: An integrated circuit (IC) device includes a network device including a first network port, a second network port, and an internal endpoint port. The IC device further includes a first processing unit including an internal end station. The first processing unit is configured to communicate with the network device using the internal endpoint port. The IC device further includes a second processing unit including a bridge management layer. The second processing unit is configured to communicate with the network device using the internal endpoint port. In various embodiments, the first processing unit and the second processing unit are configured to communicate with each other using a first internal channel.

公开(公告)号：US10862802B1

公开(公告)日：2020-12-08

申请号：US15948881

申请日：2018-04-09

Applicant: Xilinx, Inc.

Inventor： Ramesh R. Subramanian ,  Ashif Khan Mohammed

IPC: H04L12/743 ,  H04L12/46 ,  H04L12/823 ,  H04L12/931 ,  H04L29/06

Abstract: A network device includes a plurality of ports, a lookup circuit, and a traffic control circuit. The lookup circuit is configured to provide a first action for a first frame to be forwarded using a first forwarding path between a first set of two ports of the plurality of ports. The lookup circuit is further configured to and provide a second action for a second frame to be forwarded using a second forwarding path between a second set of two ports of the plurality of ports. The traffic control circuit configured to forward the first frame based on the first action and forward the second frame based on the second action.

公开(公告)号：US10402111B1

公开(公告)日：2019-09-03

申请号：US15676083

申请日：2017-08-14

Applicant: Xilinx, Inc.

Inventor： Deboleena Sakalley ,  Ramesh R. Subramanian ,  Gopikrishna Jandhyala ,  Santosh Singh ,  Seong Hwan Kim

IPC: G06F3/06 ,  G06F13/42

Abstract: A data storage system includes a bridging device. The bridging device is configured to receive, from a host through a network, a host data block size. A sub-block size is determined based on the host data block size. One or more storage devices are configured to include a plurality of storage sub-blocks each having the sub-block size. A first write command to write first host data including a first number of host data blocks to the one or more storage devices is received. The bridging device compresses the first host data to generate first compressed data, and write the first compressed data to a second number of storage sub-blocks of the one or more storage devices.