公开(公告)号：US10057976B1

公开(公告)日：2018-08-21

申请号：US15692975

申请日：2017-08-31

Applicant: Xilinx, Inc.

Inventor： Hong Shi ,  Siow Chek Tan ,  Sarajuddin Niazi

IPC: H01L23/49 ,  H01L23/64 ,  H01L23/66 ,  H05K1/02 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/552 ,  H03H7/01 ,  H01L25/065 ,  H05K1/18 ,  H01L23/538

CPC classification number: H05K1/0231 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/538 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/552 ,  H01L23/642 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/3025 ,  H03H7/0115 ,  H05K1/0216 ,  H05K1/0233 ,  H05K1/162 ,  H05K1/181 ,  H05K2201/10734 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An interface layout for a vertical interface of a first semiconductor component is disclosed. A first one or more conductors configured to carry power signals extends vertically from the first semiconductor component. A second one or more conductors configured to carry data signals extends vertically from the first semiconductor component. A third one or more conductors configured to carry ground signals extending vertically from the first semiconductor component. The first one or more conductors are further configured to shield and separate the second one or more conductors. A fourth one or more conductors extends horizontally from the first one or more conductors adjacent to and terminating proximal to the third one or more conductors. A fifth one or more conductors extending horizontally from the third one or more conductors adjacent to and terminating proximal to the first one or more conductors and the fourth one or more conductors. The fourth one or more conductors and the corresponding adjacent fifth one or more conductors form a plate capacitor.

公开(公告)号：US10038259B2

公开(公告)日：2018-07-31

申请号：US14174697

申请日：2014-02-06

Applicant: Xilinx, Inc.

Inventor： Paul Y. Wu ,  Sarajuddin Niazi ,  Raymond E. Anderson ,  Suresh Ramalingam

IPC: H05K1/11 ,  H05K1/14 ,  H01R12/71 ,  H01R43/02 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01R12/71 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5386 ,  H01L2224/16 ,  H01L2924/0002 ,  H01R43/0235 ,  Y10T29/49117 ,  H01L2924/00

Abstract: An apparatus for placement between a package and an integrated circuit board includes: an insert having: a substrate having a top side and a bottom side; a first set of pads at the top side of the substrate; a second set of pads at the bottom side of the substrate; and a plurality of vias in the substrate, the vias connecting respective pads in the first set to respective pads in the second set; wherein the insert has a thickness that is less than a spacing between the package and the integrated circuit board.

公开(公告)号：US20150222033A1

公开(公告)日：2015-08-06

申请号：US14174697

申请日：2014-02-06

Applicant: Xilinx, Inc.

Inventor： Paul Y. Wu ,  Sarajuddin Niazi ,  Raymond E. Anderson ,  Suresh Ramlingam

IPC: H01R12/71 ,  H01R43/02

CPC classification number: H01R12/71 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5386 ,  H01L2224/16 ,  H01L2924/0002 ,  H01R43/0235 ,  Y10T29/49117 ,  H01L2924/00

Abstract: An apparatus for placement between a package and an integrated circuit board includes: an insert having: a substrate having a top side and a bottom side; a first set of pads at the top side of the substrate; a second set of pads at the bottom side of the substrate; and a plurality of vias in the substrate, the vias connecting respective pads in the first set to respective pads in the second set; wherein the insert has a thickness that is less than a spacing between the package and the integrated circuit board.

Abstract translation: 用于放置在封装和集成电路板之间的装置包括：插入件，其具有：具有顶侧和底侧的基板; 在衬底的顶侧的第一组衬垫; 在衬底的底侧的第二组衬垫; 以及衬底中的多个通孔，将第一组中的各个焊盘连接到第二组中的相应焊盘的通孔; 其中插入件的厚度小于封装和集成电路板之间的间隔。