公开(公告)号：US08884804B1

公开(公告)日：2014-11-11

申请号：US14089222

申请日：2013-11-25

Applicant: Xilinx, Inc.

Inventor： Amitava Majumdar ,  Siva Charan Nimmagadda ,  Baanurathan Sadasivam ,  Richard W. Swanson ,  Yohan Frans

IPC: H03M1/50 ,  H03M1/12 ,  H03L7/081 ,  H03L7/087 ,  H03L7/089 ,  H03M1/00

CPC classification number: G04F10/005 ,  H03L7/00 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/0895 ,  H03M1/00 ,  H03M1/12 ,  H03M2201/4233

Abstract: An apparatus relating generally to time-to-digital conversion is disclosed. In this apparatus, a time-to-digital converter is coupled to a period sensor. The period sensor includes a pulse generator to generate a pulse. An integrator of the period sensor is coupled to receive the pulse to generate an analog voltage signal responsive to the pulse. The time-to-digital converter includes an analog-to-digital converter coupled to provide a digital signal associated with the analog voltage signal.

Abstract translation: 公开了一种与时间 - 数字转换相关的装置。 在该装置中，时间 - 数字转换器耦合到周期传感器。 周期传感器包括产生脉冲的脉冲发生器。 耦合周期传感器的积分器以接收脉冲以产生响应脉冲的模拟电压信号。 时间 - 数字转换器包括耦合以提供与模拟电压信号相关联的数字信号的模拟 - 数字转换器。

公开(公告)号：US11750185B2

公开(公告)日：2023-09-05

申请号：US17482336

申请日：2021-09-22

Applicant: XILINX, INC.

Inventor： Siva Charan Nimmagadda ,  Xiaobao Wang ,  Vinit Shah ,  Sabarathnam Ekambaram ,  Hari Bilash Dubey

IPC: H03K5/156 ,  H03K5/134 ,  H03K5/135 ,  G11C7/22

CPC classification number: H03K5/1565 ,  G11C7/222 ,  H03K5/134 ,  H03K5/135

Abstract: Examples describe a duty cycle correction circuit for correcting duty cycle distortion from memory. One example is an integrated circuit for correcting an input clock signal. The integrated circuit includes a first leg circuit and a second leg circuit. The first leg circuit and the second leg circuit both comprise a charging circuit and a discharging circuit. Each charging circuit comprises a first plurality of transistors and each discharging circuit comprises a second plurality of transistors. The charging circuit is coupled to the discharging circuit in series. A number of transistors of the first plurality of transistors in the first leg circuit is different from a number of transistors of the first plurality of transistors in the second leg circuit.