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公开(公告)号：US20120183040A1
公开(公告)日：2012-07-19
申请号：US13009083
申请日：2011-01-19
申请人： Xin Fang , Wei Shi , Gerald Paul Michalak
发明人： Xin Fang , Wei Shi , Gerald Paul Michalak
IPC分类号： H04N7/26
CPC分类号： H04N21/4424 , H04N21/42607
摘要： In an example, a dynamic codec allocation method is provided. The method includes receiving a plurality of datastreams and determining a respective codec loading factor for each of the datastreams. The datastreams are assigned to codecs, in order by respective codec loading factor, starting with the highest respective codec loading factor. Initially, the datastreams are assigned to a hardware codec, until the hardware codec is loaded to substantially maximum capacity. If the hardware codec is loaded to substantially maximum capacity, the remaining datastreams are assigned to a software codec. As new datastreams are received, the method repeats, and previously-assigned datastreams can be reassigned from a hardware codec to a software codec, and vice versa, based on their relative codec loading factors.
摘要翻译： 在一个示例中，提供了动态编解码器分配方法。 该方法包括接收多个数据流并确定每个数据流的相应的编解码器加载因子。 数据流被分配到编解码器，按照相应的编解码器加载因子顺序，从最高的各自的编解码器加载因子开始。 最初，数据流被分配到硬件编解码器，直到硬件编解码器被加载到基本上最大的容量。 如果硬件编解码器被加载到基本上最大的容量，剩余的数据流被分配给软件编解码器。 当接收到新的数据流时，该方法重复，并且可以基于它们的相对编解码器加载因子将先前分配的数据流从硬件编解码器重新分配到软件编解码器，反之亦然。
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公开(公告)号：US08310225B2
公开(公告)日：2012-11-13
申请号：US12353626
申请日：2009-01-14
申请人： Gerald Paul Michalak
发明人： Gerald Paul Michalak
CPC分类号： G01R31/2884 , G01R15/181 , G01R15/202 , G01R31/3025
摘要： A current sensing mechanism for use in an integrated circuit is described. In one embodiment, the integrated circuit comprises a voltage supply rail and a current sensor coupled to that voltage supply rail such that the current sensor determines the current passing through the voltage supply rail. Leads attached to the current sensor can be monitored to obtain measurements that permit determination of the current.
摘要翻译： 描述了一种用于集成电路的电流检测机构。 在一个实施例中，集成电路包括电压供应轨和耦合到该电压供应轨的电流传感器，使得电流传感器确定通过电压供应轨的电流。 可以监控连接到电流传感器的引线，以获得允许确定电流的测量。
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公开(公告)号：US09128720B2
公开(公告)日：2015-09-08
申请号：US13183129
申请日：2011-07-14
CPC分类号： G06F1/3296 , G06F1/26 , Y02D10/172
摘要： Methods and apparatus for voltage scaling are provided. In an example, an operational limit of a processor is determined by varying a supply voltage to force a processor interrupt fault and/or a processor reset. A clock frequency and the supply voltage can be maintained substantially constant for a time duration. If these operational parameters do not force the processor interrupt fault and/or the processor reset, the supply voltage is varied again, and the clock frequency and the supply voltage are maintained substantially constant for a second time duration. The variation continues until initiation of the processor interrupt fault and/or the processor reset, at which time least one of a clock frequency, the supply voltage, and a temperature are recorded as an operational limit. After determining the operational limit, the supply voltage is adjusted to within the operational limit.
摘要翻译： 提供了电压缩放的方法和装置。 在一个示例中，通过改变供电电压来强制处理器中断故障和/或处理器复位来确定处理器的操作限制。 时钟频率和电源电压可以在一段持续时间内保持基本上恒定。 如果这些操作参数不强制处理器中断故障和/或处理器复位，则电源电压再次变化，并且时钟频率和电源电压在第二持续时间内保持基本上恒定。 变化继续，直到处理器中断故障开始和/或处理器复位，此时将时钟频率，电源电压和温度中的至少一个记录为操作限制。 确定运行极限后，将电源电压调整到运行极限内。
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4.发明申请Method and Apparatus for Executing Processor Instructions Based on a Dynamically Alterable Delay 失效基于动态可变延迟执行处理器指令的方法和装置公开(公告)号：US20080046692A1
公开(公告)日：2008-02-21
申请号：US11464839
申请日：2006-08-16
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3806 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3869 , G06F9/3877
摘要： Instruction execution delay is alterable after the system design has been finalized, thus enabling the system to dynamically account for various conditions that impact instruction execution. In some embodiments, the dynamic delay is determined by an application to be executed by the processing system. In other embodiments, the dynamic delay is determined by analyzing the history of previously executed instructions. In yet other embodiments, the dynamic delay is determined by assessing the processing resources available to a given application. Regardless, the delay may be dynamically altered on a per-instruction, multiple instruction, or application basis. Processor instruction execution may be controlled by determining a first delay value for a first set of one or more instructions and a second delay value for a second set of one or more instructions. Execution of the sets of instructions is delayed based on the corresponding delay value.
摘要翻译： 指令执行延迟在系统设计完成后可以改变，从而使系统能够动态地考虑影响指令执行的各种条件。 在一些实施例中，动态延迟由处理系统要执行的应用程序确定。 在其他实施例中，通过分析先前执行的指令的历史来确定动态延迟。 在其他实施例中，通过评估给定应用可用的处理资源来确定动态延迟。 无论如何，延迟可以在每个指令，多个指令或应用程序的基础上动态地改变。 处理器指令执行可以通过确定一个或多个指令的第一组的第一延迟值和第二组一个或多个指令的第二延迟值来控制。 基于相应的延迟值来延迟指令集的执行。
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5.发明申请Method of Associating Groups of Classified Source Addresses with Vibration Patterns 有权将分类源地址组与振动模式相关联的方法公开(公告)号：US20070176742A1
公开(公告)日：2007-08-02
申请号：US11553600
申请日：2006-10-27
CPC分类号： H04M19/04 , H04M1/57 , H04M1/72547 , H04M19/044 , H04M19/047
摘要： In a meeting or group event, people having a portable device, such as a cell phone or pager, may wish to be discretely notified when an important message is received, an urgent call comes in from a selected person or a selected group of people, or to be alerted to an upcoming important event without any audible alert to disturb the meeting or group event. To convey such a notification, a tactile alert is provided by vibrating the portable device according to a unique vibration pattern associated with the received communication. When a communication is received, a group identification (ID) is assigned based on the communication being a member of a classified group of source addresses. The portable device associates the group ID with a unique vibration pattern. To provide the alert, the portable device is vibrated according to the unique vibration pattern.
摘要翻译： 在会议或小组活动中，具有诸如蜂窝电话或寻呼机的便携式设备的人可能希望在收到重要消息时离散地通知来自所选择的人或所选人群的紧急呼叫， 或者提醒未来的重要事件而没有任何可听见的警报来打扰会议或团体活动。 为了传达这种通知，通过根据与接收的通信相关联的唯一振动模式振动便携式设备来提供触觉警报。 当接收到通信时，基于作为分类的源地址组的成员的通信来分配组标识（ID）。 便携式设备将组ID与唯一的振动模式相关联。 为了提供警报，便携式设备根据独特的振动模式而振动。
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公开(公告)号：US08797095B2
公开(公告)日：2014-08-05
申请号：US12750123
申请日：2010-03-30
CPC分类号： G05F1/462 , G06F1/3203 , G06F1/3234 , G06F1/324 , G06F1/3296 , H03K3/012 , Y02D10/126 , Y02D10/172
摘要： Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variation conditions to avoid or reduce voltage margin. In one embodiment, the AVS includes an AVS database. The AVS database can be configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The AVS database allows rapid voltage level decisions. The voltage levels stored in the AVS database may be initial, minimum, learned, populated, explored, backed out, temperature-based, and/or age-based voltage levels according to disclosed embodiments to further avoid or reduce voltage margin. An AVS module may be a software-based module that consults the AVS database to make voltage level decisions. Providing the AVS module as a software-based module may allow flexibility in configuring the AVS module and/or the AVS database.
摘要翻译： 自适应电压缩放器（AVS），系统和相关方法被公开。 AVS被配置为基于目标工作频率和延迟变化条件自适应地调整为功能电路供电的电压电平，以避免或减少电压裕度。 在一个实施例中，AVS包括AVS数据库。 AVS数据库可以配置为存储功能电路的各种工作频率的电压电平，以避免或减少电压裕度。 AVS数据库允许快速的电压电平决定。 根据所公开的实施例，存储在AVS数据库中的电压电平可以是初始，最小，学习，填充，探测，退出，基于温度和/或基于年龄的电压电平，以进一步避免或降低电压裕度。 AVS模块可以是参考AVS数据库以进行电压电平决定的基于软件的模块。 将AVS模块提供为基于软件的模块可以允许在配置AVS模块和/或AVS数据库方面的灵活性。
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公开(公告)号：US20130212334A1
公开(公告)日：2013-08-15
申请号：US13369548
申请日：2012-02-09
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F9/38
摘要： A run-time delay of a memory is measured, a run-time duration of a routine is determined, and an optimal run-time preload distance for the routine is determined based on the measured run-time memory delay and the determined run-time duration of the routine. Optionally, the run-time duration of the routine can be determined by measuring a run-time duration, and optionally the run-time duration can be determined based on a database of run-time delay for operations of the routine. Optionally, the optimal run-time preload distance is used in performing a loop of the routines.
摘要翻译： 测量存储器的运行时间延迟，确定例程的运行时间持续时间，并且基于所测量的运行时间存储器延迟和确定的运行时间来确定该程序的最佳运行时预加载距离 例程的持续时间 可选地，可以通过测量运行时间持续时间来确定例程的运行时间长度，并且可选地，可以基于用于该例程的操作的运行时间延迟的数据库来确定运行时间持续时间。 可选地，最佳运行时预加载距离用于执行例程的循环。
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公开(公告)号：US20110080202A1
公开(公告)日：2011-04-07
申请号：US12750123
申请日：2010-03-30
IPC分类号： H03H11/26
CPC分类号： G05F1/462 , G06F1/3203 , G06F1/3234 , G06F1/324 , G06F1/3296 , H03K3/012 , Y02D10/126 , Y02D10/172
摘要： Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variation conditions to avoid or reduce voltage margin. In one embodiment, the AVS includes an AVS database. The AVS database can be configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The AVS database allows rapid voltage level decisions. The voltage levels stored in the AVS database may be initial, minimum, learned, populated, explored, backed out, temperature-based, and/or age-based voltage levels according to disclosed embodiments to further avoid or reduce voltage margin. An AVS module may be a software-based module that consults the AVS database to make voltage level decisions. Providing the AVS module as a software-based module may allow flexibility in configuring the AVS module and/or the AVS database.
摘要翻译： 自适应电压缩放器（AVS），系统和相关方法被公开。 AVS被配置为基于目标工作频率和延迟变化条件自适应地调整为功能电路供电的电压电平，以避免或减少电压裕度。 在一个实施例中，AVS包括AVS数据库。 AVS数据库可以配置为存储功能电路的各种工作频率的电压电平，以避免或减少电压裕度。 AVS数据库允许快速的电压电平决定。 根据所公开的实施例，存储在AVS数据库中的电压电平可以是初始，最小，学习，填充，探测，退出，基于温度和/或基于年龄的电压电平，以进一步避免或降低电压裕度。 AVS模块可以是参考AVS数据库以进行电压电平决定的基于软件的模块。 将AVS模块提供为基于软件的模块可以允许在配置AVS模块和/或AVS数据库方面的灵活性。
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公开(公告)号：US20100176793A1
公开(公告)日：2010-07-15
申请号：US12353626
申请日：2009-01-14
申请人： Gerald Paul Michalak
发明人： Gerald Paul Michalak
IPC分类号： G01R33/07
CPC分类号： G01R31/2884 , G01R15/181 , G01R15/202 , G01R31/3025
摘要： A current sensing mechanism for use in an integrated circuit is described. In one embodiment, the integrated circuit comprises a voltage supply rail and a current sensor coupled to that voltage supply rail such that the current sensor determines the current passing through the voltage supply rail. Leads attached to the current sensor can be monitored to obtain measurements that permit determination of the current.
摘要翻译： 描述了一种用于集成电路的电流检测机构。 在一个实施例中，集成电路包括电压供应轨和耦合到该电压供应轨的电流传感器，使得电流传感器确定通过电压供应轨的电流。 可以监控连接到电流传感器的引线，以获得允许确定电流的测量。
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10.发明授权System and method to reduce dynamic RAM power consumption via the use of valid data indicators 有权通过使用有效的数据指标来减少动态RAM功耗的系统和方法公开(公告)号：US07590021B2
公开(公告)日：2009-09-15
申请号：US11828569
申请日：2007-07-26
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40622
摘要： A DRAM or SDRAM component maintains an indicator that indicates whether or not an independently refreshable memory unit of a DRAM array, such as a row, contains valid data. When a refresh operation is directed to the associated memory, the refresh operation is suppressed if the memory does not contain valid data. Significant power savings may be realized by suppressing refresh operations directed to invalid data.
摘要翻译： DRAM或SDRAM组件保持指示器，其指示诸如行的DRAM阵列的独立可刷新的存储器单元是否包含有效数据。 当刷新操作指向相关联的存储器时，如果存储器不包含有效数据，则刷新操作被抑制。 可以通过抑制针对无效数据的刷新操作来实现显着的功率节省。
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