公开(公告)号：US20130119524A1

公开(公告)日：2013-05-16

申请号：US13678503

申请日：2012-11-15

Applicant: Xintec Inc.

Inventor： Yuan-Ru CHAN

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/4952 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/93 ,  H01L2224/97 ,  H01L2924/10158 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2924/00

Abstract: A chip package includes: a substrate having a first surface and a second surface; a device region disposed in or on the substrate; a conducting pad disposed in the substrate or on the first surface, wherein the conducting pad is electrically connected to the device region; a hole extending from the second surface towards the first surface of the substrate; a wiring layer disposed on the second surface of the substrate and extending towards the first surface of the substrate along a sidewall of the hole to make electrical contact with the conducting pad, wherein a thickness of a first portion of the wiring layer located directly on the conducting pad is smaller than a thickness of the second portion of the wiring layer located directly on the sidewall of the hole; and an insulating layer disposed between the substrate and the wiring layer.

Abstract translation: 芯片封装包括：具有第一表面和第二表面的基板; 设置在所述基板中或所述基板上的器件区域; 导电焊盘，设置在所述衬底中或所述第一表面上，其中所述导电焊盘电连接到所述器件区域; 从所述第二表面朝向所述基板的所述第一表面延伸的孔; 布线层，其布置在所述基板的第二表面上并且沿着所述孔的侧壁朝向所述基板的所述第一表面延伸以与所述导电垫电接触，其中所述布线层的第一部分的厚度直接位于所述 导电焊盘小于直接位于孔的侧壁上的布线层的第二部分的厚度; 以及设置在所述基板和所述布线层之间的绝缘层。