公开(公告)号：US20240098989A1

公开(公告)日：2024-03-21

申请号：US17948549

申请日：2022-09-20

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Zhengliang Xia ,  Wenbin Zhou ,  Zongliang Huo ,  Zhaohui Tang

IPC分类号： H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

CPC分类号： H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

摘要： A semiconductor device includes a plurality of memory blocks. Each memory block includes a memory deck including interleaved first conductor layers and first dielectric layers, and a separation structure extending to separate two adjacent memory blocks. Each separation structure includes a dielectric stack including interleaved third dielectric layers and fourth dielectric layers. The third dielectric layers are in contact with the first dielectric layers, and the fourth dielectric layers are in contact with the first conductor layers.

公开(公告)号：US20240196621A1

公开(公告)日：2024-06-13

申请号：US18092109

申请日：2022-12-30

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Zongliang Huo ,  Lei Xue ,  Wenbin Zhou ,  Wei Xu ,  Yanwei Shi ,  Zhengliang Xia ,  Han Yang ,  Xinwei Zou ,  Zhaohui Tang ,  Jiaji Wu ,  Cheng Chen

IPC分类号： H10B43/40 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC分类号： H10B43/40 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

摘要： A semiconductor device includes a base and a stack structure. The base includes a first surface defining at least one memory plane region. The stack structure is disposed on the first surface, and includes a first portion located at the edge of the memory plane region and a second portion different from the first portion. The first portion includes first contact structures penetrating through the stack structure in a first direction and extending to the base. The second portion includes second contact structures electrically connected with corresponding gate conductor layers in the stack structure. A top surface of the first contact structure away from the base is flush with a top surface of the second contact structure away from the base.

公开(公告)号：US20230121962A1

公开(公告)日：2023-04-20

申请号：US18083927

申请日：2022-12-19

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Zhaohui Tang ,  Lei Zhang ,  Yuting Zhou ,  Si Qiao

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L23/528 ,  H01L29/788 ,  H01L29/792 ,  H10B41/20 ,  H10B43/20 ,  H01L23/522

摘要： A method for manufacturing a semiconductor device is provided. The method includes the following. A substrate is provided. A stacked structure is formed on the substrate. The stacked structure includes first material layers and gate layers that are alternatively stacked. The stacked structure includes a giant block (GB) region and a stair-step region. A third material layer is formed on an upper surface of the GB region and an upper surface of the stair-step region. A fourth material layer filling the stair-step region and covering the GB region is formed. At least one contact structure is located in the stair-step region. Each of the at least one contact structure penetrates the third material layer and is connected with a respective one of the gate layers.

公开(公告)号：US20230114522A1

公开(公告)日：2023-04-13

申请号：US18079827

申请日：2022-12-12

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： Zhaohui Tang

IPC分类号： H10B43/20 ,  H10B43/35 ,  H01L21/304 ,  H01L21/02

摘要： A three-dimensional memory device and a method for manufacturing the same are provided. The method includes steps as follows. A semiconductor structure including a substrate and a stacked structure on the substrate is provided. The stacked structure includes alternately stacked gate layers and dielectric layers, or alternately stacked dummy gate layers and dielectric layers. The dummy gate layers are replaceable by the gate layers. A groove is formed in a gate line slit region of the stacked structure. The groove penetrates through the gate layers and multiple layers of the dielectric layers, or through the dummy gate layers and multiple layers of the dielectric layers. An insulating layer is formed on a surface of the stacked structure and in the groove. A depression is formed on a surface of the insulating layer above the groove away from the substrate. The insulating layer is polished to flatten the depression.