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公开(公告)号：US20230326537A1
公开(公告)日：2023-10-12
申请号：US18122928
申请日：2023-03-17
发明人： Zhipeng Dong , Ke Liang
CPC分类号： G11C16/3459 , G11C16/102
摘要： A memory device includes a memory array including memory blocks, and a control circuit coupled to the memory array. The control circuit is configured to when multi-pass program operations are performed, during a non-last pass program of the memory cells in a first memory sub-block of a first memory block, determine verify loop counts of verify operations after programming the memory cells in the first memory sub-block of the first memory block to one or more first target program states; and when programming the memory cells in a second memory sub-block of the first memory block to the one or more first target program states using the same program and verify conditions as for the first memory sub-block of the first memory block, during the non-last pass program, not perform at least the verify operation corresponding to the last of the verify loop counts.
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公开(公告)号：US11705202B2
公开(公告)日：2023-07-18
申请号：US17499154
申请日：2021-10-12
发明人： Zhipeng Dong , Venkatagirish Nagavarapu , Haibo Li
CPC分类号： G11C16/10 , G11C16/3459
摘要： A memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of strings. A method of programming the memory device includes programming a first row of the memory cells. The method also includes, after programing the first row of the memory cells, programming a second row of the memory cells. The second row is adjacent to the first row in a first string direction. The method further includes, after programming the second row of the memory cells, programming a third row of the memory cells. The third row is two rows apart from the second row in a second string direction opposite to the first string direction.
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公开(公告)号：US20240079056A1
公开(公告)日：2024-03-07
申请号：US17951794
申请日：2022-09-23
发明人： Zhipeng Dong , Ying Cui , Li Xiang
CPC分类号： G11C16/0433 , G11C16/08 , G11C16/14
摘要： A memory device, an operating method thereof, a system, and a non-transitory tangible storage medium are disclosed. The memory device includes a source line (SL), a bit line (BL), a memory string, a word line, a select line and a peripheral circuit. The memory string includes a memory cell and a select transistor including a storage layer. The word line is coupled to the memory cell. The select line is coupled to the select transistor. The peripheral circuit is coupled to the SL, the BL, the select line, and the word line. The peripheral circuit is configured to: apply a first voltage to the select line; and apply a second voltage to the SL and/or the BL, in which a first peak level of the first voltage is greater than a second peak level of second voltage.
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公开(公告)号：US11200953B2
公开(公告)日：2021-12-14
申请号：US17172015
申请日：2021-02-09
发明人： Zhipeng Dong , Venkatagirish Nagavarapu , Haibo Li
摘要： A memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of strings. A method of programming the memory device includes programming a first row of the memory cells. The method also includes, after programing the first row of the memory cells, programming a second row of the memory cells. The second row is adjacent to the first row in a first string direction. The method further includes, after programming the second row of the memory cells, programming a third row of the memory cells. The third row is two rows apart from the second row in a second string direction opposite to the first string direction.
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公开(公告)号：US20240355399A1
公开(公告)日：2024-10-24
申请号：US18226191
申请日：2023-07-25
发明人： Zhipeng Dong , Li Xiang , Zhuo Chen , Shuai Wang , Chunyuan Hou
CPC分类号： G11C16/3445 , G11C16/16
摘要： Implementations of the present disclosure provide a memory device, an operation method thereof, and a memory system. The memory device may include a memory cell array including a plurality of blocks. The memory device may include a peripheral circuit coupled to the memory cell array. The peripheral circuit may be configured to apply a plurality of different erasure verification voltages to a selected block among the plurality of blocks after applying a first effective erasure voltage to the selected block. The peripheral circuit may be configured to determine a second effective erasure voltage applied to the selected block according to a plurality of erasure verification results corresponding to the plurality of different erasure verification voltages. The second effective erasure voltage may be greater than the first effective erasure voltage.
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公开(公告)号：US11538537B2
公开(公告)日：2022-12-27
申请号：US17232059
申请日：2021-04-15
发明人： Zhipeng Dong , Min Zhang , Haibo Li
摘要： A memory device is provided. The memory device includes an array of memory cells arranged, a plurality of word lines, and a peripheral circuit configured to perform multi-pass programming on a selected row of memory cells coupled to a selected word line. The multi-pass programming includes a plurality of programming passes. Each of the programming passes includes a programming operation and a verify operation. To perform the multi-pass programming, the peripheral circuit is configured to, in a non-last programming pass of memory cells, perform a negative gate stress (NGS) operation on a memory cell in the selected row of memory cells between the programming operation and the verify operation; and at a same time, perform a NGS operation on a memory cell in an unselected row of memory cells coupled to an unselected word line of the word lines. The unselected word line is adjacent to the selected word line.
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公开(公告)号：US20220028458A1
公开(公告)日：2022-01-27
申请号：US17499154
申请日：2021-10-12
发明人： Zhipeng Dong , Venkatagirish Nagavarapu , Haibo Li
摘要： A memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of strings. A method of programming the memory device includes programming a first row of the memory cells. The method also includes, after programing the first row of the memory cells, programming a second row of the memory cells. The second row is adjacent to the first row in a first string direction. The method further includes, after programming the second row of the memory cells, programming a third row of the memory cells. The third row is two rows apart from the second row in a second string direction opposite to the first string direction.
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公开(公告)号：US12068035B2
公开(公告)日：2024-08-20
申请号：US17944658
申请日：2022-09-14
发明人： Zhipeng Dong
CPC分类号： G11C16/102 , G11C16/0433 , G11C16/08 , G11C16/24
摘要： A memory, a programming method, and a memory system are provided. The programming method includes programming a selected memory cell string according to a programming sequence; applying, when programming a memory cell in the selected memory cell string that is coupled to a selected non-edge word line in a plurality of word lines, a first pass voltage to edge word lines in the plurality of word lines; and applying a second pass voltage to a non-edge word line adjacent to the edge word lines. The edge word lines are at least one word line in the plurality of word lines adjacent to the source line or to the bit line; the non-edge word lines are word lines in the plurality of word lines other than the edge word lines; and the selected non-edge word line is not adjacent to the edge word lines.
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公开(公告)号：US12057176B2
公开(公告)日：2024-08-06
申请号：US17931764
申请日：2022-09-13
发明人： Zhipeng Dong , Ke Liang , Liang Qiao
摘要： The present disclosure provides a method for controlling a 3D NAND memory using a read operation. The method can include increasing a voltage to a plurality of top select gates, with respect to a first reference voltage level, during a pre-pulse period of the read operation prior to a read period of the read operation. The method can also include increasing a voltage to a plurality of word lines, with respect to a second reference voltage level, during the pre-pulse period. The method can also include decreasing a voltage to a bit line, with respect to the first voltage, during the pre-pulse period. The method can also include applying no voltage change to a bottom select gate during the pre-pulse period.
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公开(公告)号：US12056355B2
公开(公告)日：2024-08-06
申请号：US17940652
申请日：2022-09-08
发明人： Zhipeng Dong , Ying Huang , Manxi Wang , Hongtao Liu , Ling Chu , Ke Liang
IPC分类号： G06F3/06
CPC分类号： G06F3/0608 , G06F3/0653 , G06F3/0679
摘要： This disclosure provides a memory device, a memory system, and an operation method. The memory device includes a memory array having a plurality of memory blocks and a control circuit coupled to the memory array and used to control the memory array. The control circuit is configured to determine a first average value of threshold voltages of bottom dummy cells in an unused memory block, determine a difference value between the first average value and a first reference value, and judge based on the difference value when bottom dummy cells in the memory block are to be programmed so that the first average value reaches a first threshold.
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