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    THREE-DIMENSIONAL NAND MEMORY DEVICE AND METHOD OF FORMING THE SAME
    4.
    发明申请
    THREE-DIMENSIONAL NAND MEMORY DEVICE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20220037354A1

    公开(公告)日：2022-02-03

    申请号：US17451583

    申请日：2021-10-20

    申请人： Yangtze Memory Technologies Co., Ltd.

    发明人： Zhong ZHANG ,  Zhongwang SUN ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zhi ZHANG

    IPC分类号： H01L27/11582 ,  G11C8/14 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565

    摘要： In a method for fabricating a semiconductor device, an initial stack of alternatingly sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. A connection region, a first staircase region, and a second staircase region are patterned in the initial stack. The first staircase region is shaped in the initial stack to form a first staircase, and the second staircase region is shaped in the initial stack to form a second staircase. The first staircase is formed in a first block of the initial stack and extends between first array regions of the first block. The second staircase is formed in a second block of the initial stack and extends between second array regions of the second block. The connection region is formed in the initial stack between the first staircase and the second staircase.

    CONTACT STRUCTURES FOR THREE-DIMENSIONAL MEMORY DEVICE
    6.
    发明申请
    CONTACT STRUCTURES FOR THREE-DIMENSIONAL MEMORY DEVICE 有权

    公开(公告)号：US20230086425A1

    公开(公告)日：2023-03-23

    申请号：US17993600

    申请日：2022-11-23

    申请人： Yangtze Memory Technologies Co., Ltd.

    发明人： Zhongwang SUN ,  Guangji LI ,  Kun ZHANG ,  Ming HU ,  Jiwei CHENG ,  Shijin LUO ,  Kun BAO ,  Zhiliang XIA

    IPC分类号： H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11529

    摘要： Embodiments of contact structures of a three-dimensional memory device and fabrication method thereof are disclosed. The three-dimensional memory structure includes a film stack disposed on a substrate, wherein the film stack includes a plurality of conductive and dielectric layer pairs, each conductive and dielectric layer pair having a conductive layer and a first dielectric layer. The three-dimensional memory structure also includes a staircase structure formed in the film stack, wherein the staircase structure includes a plurality of steps, each staircase step having two or more conductive and dielectric layer pairs. The three-dimensional memory structure further includes a plurality of coaxial contact structures formed in a first insulating layer over the staircase structure, wherein each coaxial contact structure includes one or more conductive and insulating ring pairs and a conductive core, each conductive and insulating ring pair having a conductive ring and an insulating ring.

    MEMORY DEVICE AND METHOD FOR FORMING THE SAME
    7.
    发明申请
    MEMORY DEVICE AND METHOD FOR FORMING THE SAME 有权

    公开(公告)号：US20220037490A1

    公开(公告)日：2022-02-03

    申请号：US17500340

    申请日：2021-10-13

    申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    发明人： Zhongwang SUN ,  Zhong ZHANG ,  Lei LIU ,  Wenxi ZHOU ,  Zhiliang XIA

    IPC分类号： H01L29/423 ,  H01L27/11529 ,  H01L21/28 ,  H01L27/11573

    摘要： Memory device includes a bottom-select-gate (BSG) structure. Cut slits are formed vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.

    MEMORY DEVICE AND METHOD FOR FORMING THE SAME
    8.
    发明申请
    MEMORY DEVICE AND METHOD FOR FORMING THE SAME 有权

    公开(公告)号：US20210366917A1

    公开(公告)日：2021-11-25

    申请号：US16900511

    申请日：2020-06-12

    申请人： Yangtze Memory Technologies Co., Ltd.

    发明人： Zhongwang SUN ,  Rui SU ,  Zhong ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA

    IPC分类号： H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582

    摘要： Memory device includes a bottom-select-gate (BSG) structure including cut slits vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. A first gate-line slit is between first and second finger regions and includes gate-line sub-slits. The first finger region is divided into a first string region and a second string region by a first cut-slit, formed in the first finger region along a second lateral direction and further extended into at least the second finger region along the first lateral direction. At least one BSG defined by the first cut-slit is located in at least the second finger region to connect to cell strings in the first string region through an inter-portion between adjacent gate-line sub-slits.

    CONTACT STRUCTURES FOR THREE-DIMENSIONAL MEMORY
    9.
    发明申请
    CONTACT STRUCTURES FOR THREE-DIMENSIONAL MEMORY 有权

    公开(公告)号：US20210287991A1

    公开(公告)日：2021-09-16

    申请号：US16875180

    申请日：2020-05-15

    申请人： Yangtze Memory Technologies Co., Ltd.

    发明人： Zhongwang SUN ,  Zhong ZHANG ,  Wenxi ZHOU ,  Lei LIU ,  Zhiliang XIA

    IPC分类号： H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/321 ,  H01L21/768

    摘要： Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.

    3D NAND MEMORY DEVICE AND METHOD OF FORMING THE SAME
    10.
    发明申请
    3D NAND MEMORY DEVICE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20210265268A1

    公开(公告)日：2021-08-26

    申请号：US17113519

    申请日：2020-12-07

    申请人： Yangtze Memory Technologies Co., Ltd.

    发明人： Rui SU ,  Zhongwang SUN ,  Wenxi ZHOU ,  Zhiliang XIA

    IPC分类号： H01L23/528 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L23/522 ,  H01L21/768

    摘要： A semiconductor device is provided. The semiconductor device includes a substrate, a stack of word line layers and insulating layers that are stacked alternatingly over the substrate, and channel structures formed in a first array region and a second array region of the stack. The first array region and the second array region are positioned at opposing sides of the stack. A first staircase is formed in a connection region of the stack over the substrate. The connection region is arranged between the first and second array regions and the first staircase has non-quadrilateral treads. A second staircase is formed in the connection region of the stack over the substrate and the second staircase has non-quadrilateral treads. The connection region in the stack includes a separation region between the first and second staircases.