公开(公告)号：US07663184B1

公开(公告)日：2010-02-16

申请号：US12183358

申请日：2008-07-31

申请人： Yao-Fu Chan ,  Ta-Kang Chu ,  Jung-Chuan Ting ,  Cheng-Ming Yih

发明人： Yao-Fu Chan ,  Ta-Kang Chu ,  Jung-Chuan Ting ,  Cheng-Ming Yih

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11521 ,  H01L27/11519 ,  H01L29/7881

摘要： A memory and a method of fabricating the same are provided. The memory is disposed on a substrate in which a plurality of trenches is arranged in parallel. The memory includes a gate structure and a doped region. The gate structure is disposed between the trenches. The doped region is disposed at one side of the gate structure, in the substrate between the trenches and in the sidewalls and bottoms of the trenches. The top surface of the doped region in the substrate between the trenches is lower than the surface of the substrate under the gate structure by a distance, and the distance is greater than 300 Å.

摘要翻译： 提供了一种存储器及其制造方法。 存储器设置在其中多个沟槽平行布置的衬底上。 存储器包括栅极结构和掺杂区域。 栅极结构设置在沟槽之间。 掺杂区域设置在栅极结构的一侧，位于沟槽之间的衬底中以及沟槽的侧壁和底部中。 在沟槽之间的衬底中的掺杂区的顶表面比栅极结构下的衬底表面低一个距离，并且距离大于300。

公开(公告)号：US20100025750A1

公开(公告)日：2010-02-04

申请号：US12183358

申请日：2008-07-31

申请人： Yao-Fu Chan ,  Ta-Kang Chu ,  Jung-Chuan Ting ,  Cheng-Ming Yih

发明人： Yao-Fu Chan ,  Ta-Kang Chu ,  Jung-Chuan Ting ,  Cheng-Ming Yih

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/11519 ,  H01L29/7881

摘要： A memory and a method of fabricating the same are provided. The memory is disposed on a substrate in which a plurality of trenches is arranged in parallel. The memory includes a gate structure and a doped region. The gate structure is disposed between the trenches. The doped region is disposed at one side of the gate structure, in the substrate between the trenches and in the sidewalls and bottoms of the trenches. The top surface of the doped region in the substrate between the trenches is lower than the surface of the substrate under the gate structure by a distance, and the distance is greater than 300 Å.

摘要翻译： 提供了一种存储器及其制造方法。 存储器设置在其中多个沟槽平行布置的衬底上。 存储器包括栅极结构和掺杂区域。 栅极结构设置在沟槽之间。 掺杂区域设置在栅极结构的一侧，位于沟槽之间的衬底中以及沟槽的侧壁和底部中。 在沟槽之间的衬底中的掺杂区的顶表面比栅极结构下的衬底表面低一个距离，并且距离大于300。

公开(公告)号：US08017480B2

公开(公告)日：2011-09-13

申请号：US11423842

申请日：2006-06-13

申请人： Chen-Chin Liu ,  Chun-Pei Wu ,  Ta-Kang Chu ,  Yao-Fu Chan

发明人： Chen-Chin Liu ,  Chun-Pei Wu ,  Ta-Kang Chu ,  Yao-Fu Chan

IPC分类号： H01L21/8234

CPC分类号： H01L29/4234 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/42324

摘要： A method for fabricating a floating gate memory device comprises using thin buried diffusion regions with increased encroachment by a buried diffusion oxide layer into the buried diffusion layer and underneath the tunnel oxide under the floating gate. Further, the floating gate polysilicon layer has a larger height than the buried diffusion height. The increased step height of the gate polysilicon layer to the buried diffusion layer, and the increased encroachment of the buried diffusion oxide, can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.

摘要翻译： 一种用于制造浮动栅极存储器件的方法，包括使用较薄的掩埋扩散区，其中埋入扩散氧化物层的埋入扩大到掩埋扩散层内并在浮动栅极下方的隧道氧化物下面。 此外，浮置栅极多晶硅层具有比掩埋扩散高度更大的高度。 栅极多晶硅层对掩埋扩散层的阶梯高度增加以及掩埋扩散氧化物的侵蚀增加，可以产生较高的GCR，同时仍然允许使用虚拟接地阵列设计减小电池尺寸。

公开(公告)号：US20070284644A1

公开(公告)日：2007-12-13

申请号：US11423842

申请日：2006-06-13

申请人： Chen-Chin Liu ,  Chun-Pei Wu ,  Ta-Kang Chu ,  Yao-Fu Chan

发明人： Chen-Chin Liu ,  Chun-Pei Wu ,  Ta-Kang Chu ,  Yao-Fu Chan

IPC分类号： H01L29/76

CPC分类号： H01L29/4234 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/42324

摘要： A method for fabricating a floating gate memory device comprises using thin buried diffusion regions with increased encroachment by a buried diffusion oxide layer into the buried diffusion layer and underneath the tunnel oxide under the floating gate. Further, the floating gate polysilicon layer has a eight than the buried diffusion height. The increased step height of the gate polysilicon layer to the buried diffusion layer, and the increased encroachment of the buried diffusion oxide, can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.

摘要翻译： 一种用于制造浮动栅极存储器件的方法，包括使用较薄的掩埋扩散区，其中埋入扩散氧化物层的埋入扩大到掩埋扩散层内并在浮动栅极下方的隧道氧化物下面。 此外，浮栅多晶硅层的掩埋扩散高度为8。 栅极多晶硅层对掩埋扩散层的阶梯高度增加以及掩埋扩散氧化物的侵蚀增加，可以产生较高的GCR，同时仍然允许使用虚拟接地阵列设计减小电池尺寸。