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1.发明授权Method and apparatus for analyzing a layout using an instance-based representation 有权用于使用基于实例的表示来分析布局的方法和装置公开(公告)号：US06560766B2
公开(公告)日：2003-05-06
申请号：US09917526
申请日：2001-07-26
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： One embodiment of the invention provides a system that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout. The system operates by receiving a representation of the layout, wherein the representation defines a plurality of nodes that include one or more geometrical features. Next, the system converts the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout, wherein each node instance can be further processed without having to consider effects of external factors on the node instance. The system then performs an further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.
摘要翻译： 本发明的一个实施例提供一种系统，其使用包括布局的一组几何特征的基于实例的表示来分析与半导体芯片上的电路相关的布局。 系统通过接收布局的表示来操作，其中所述表示定义包括一个或多个几何特征的多个节点。 接下来，系统通过识别布局中相同的节点实例的多次发生，将表示转换为基于实例的表示，其中可以进一步处理每个节点实例而不必考虑外部因素对节点实例的影响。 然后，系统通过仅处理每个节点实例一次对基于实例的表示进行进一步的处理，由此在布局中的多个节点实例的出现上不必重复该处理。
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公开(公告)号：US06721928B2
公开(公告)日：2004-04-13
申请号：US10323565
申请日：2002-12-17
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： The present invention uses an instance based (IB) representation to reduce the time required for verifying a transformed layout that was generated from a reference layout. Specifically, an IB based representation is generated from the reference layout. The IB based representation includes sets of instance cells that include a master instance cell and slave instance cells. Only a subset of each set of instance cell needs to be simulated to verify the transformed layout.
摘要翻译： 本发明使用基于实例的（IB）表示来减少验证从参考布局生成的经转换的布局所需的时间。 具体来说，从参考布局生成基于IB的表示。 基于IB的表示包括包括主实例单元和从实例单元的实例单元的集合。 需要模拟每组实例单元的一个子集，以验证转换后的布局。
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3.发明授权Method and apparatus for exposing a wafer using multiple masks during an integrated circuit manufacturing process 有权在集成电路制造过程中使用多个掩模曝光晶片的方法和装置公开(公告)号：US06795168B2
公开(公告)日：2004-09-21
申请号：US10117838
申请日：2002-04-08
IPC分类号： G03B2754
CPC分类号： G03F7/70208 , G03F7/70283
摘要： One embodiment of the invention provides a system that facilitates exposing a wafer through at least two masks during an integrated circuit manufacturing process. The system includes a radiation source and two or more illuminators. Each of these illuminators receives radiation from the radiation source, and uses the radiation to illuminate a reticle holder. The radiation that passes through each reticle holder is then combined in an optical combiner, before passing through an imaging optics, which projects the combined radiation onto a semiconductor wafer.
摘要翻译： 本发明的一个实施例提供一种在集成电路制造过程中有助于使晶片通过至少两个掩模的系统。 该系统包括辐射源和两个或更多个照明器。 这些照明器中的每一个接收来自辐射源的辐射，并且使用辐射来照射标线架座。 然后通过每个光罩保持器的辐射在光合成器中通过成像光学器件，成像光学器件将组合的辐射投影到半导体晶片上。
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公开(公告)号：US06584609B1
公开(公告)日：2003-06-24
申请号：US09514551
申请日：2000-02-28
IPC分类号： G06F1750
CPC分类号： G03F1/70 , G03F1/36 , G06F17/5068
摘要： A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.
摘要翻译： 公开了一种半导体布局测试和校正系统。 该系统结合基于规则的光学邻近校正和基于模型的光学邻近校正，以便测试和校正半导体布局。 在第一实施例中，半导体布局首先由基于规则的光学邻近校正系统处理，然后由基于模型的光学邻近校正系统进行处理。 在另一个实施例中，系统首先使用基于规则的光学邻近校正系统处理半导体布局，然后使用基于模型的光学邻近校正系统来选择性地处理困难的特征。 在另一个实施例中，系统使用基于规则的光学邻近校正系统或基于模型的光学邻近校正系统选择性地处理半导体布局的各种特征。
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公开(公告)号：US06988259B2
公开(公告)日：2006-01-17
申请号：US10327454
申请日：2002-12-20
CPC分类号： G03F1/70 , G03F1/36 , G06F17/5068
摘要： A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.
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6.发明授权Conflict sensitive compaction for resolving phase-shift conflicts in layouts for phase-shifted features 有权用于解决相移特征的布局中的相移冲突的冲突敏感压缩公开(公告)号：US06622288B1
公开(公告)日：2003-09-16
申请号：US09823146
申请日：2001-03-29
IPC分类号： G06F1750
CPC分类号： G03F1/30
摘要： Techniques for forming a design layout with phase-shifted features, such as an integrated circuit layout, include receiving information about a particular phase-shift conflict in a first physical design layout. The information indicates one or more features logically associated with the particular phase-shift conflict. Then the first physical design layout is adjusted based on that information to produce a second design layout. The adjustments rearrange features in a unit of the design layout to collect free space around a selected feature associated with the phase-shift conflict. With these techniques, a unit needing more space for additional shifters can obtain the needed space during the physical design process making the adjustment. The needed space so obtained allows the fabrication design process to avoid or resolve phase conflicts while forming a fabrication layout, such as a mask, for substantiating the design layout in a printed features layer, such as in an actual integrated circuit.
摘要翻译： 用于形成具有诸如集成电路布局的相移特征的设计布局的技术包括在第一物理设计布局中接收关于特定相移冲突的信息。 该信息指示与特定相移冲突逻辑关联的一个或多个特征。 然后根据该信息调整第一个物理设计布局以产生第二个设计布局。 调整重新排列设计布局中的功能，以收集与相移冲突相关的所选功能周围的可用空间。 利用这些技术，在进行调整的物理设计过程中，需要更多空间的单元可以获得额外的移位器的空间。 如此获得的所需空间允许制造设计过程避免或解决相位冲突，同时形成诸如掩模的制造布局，用于证实印刷特征层（例如在实际集成电路中）的设计布局。
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公开(公告)号：US07014955B2
公开(公告)日：2006-03-21
申请号：US09941453
申请日：2001-08-28
摘要： Automated techniques for identifying dummy/main features on a mask layer are provided. In a multiple mask layer technique, the definition of a dummy/main feature can be based on connectivity information or functional association information. In a geometry technique, the definition of a dummy/main feature can be based on a feature size, a feature shape, a pattern of features, or a proximity of a feature to a neighboring feature. In one embodiment, multiple definitions and multiple techniques can be used.
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8.发明授权Method of incorporating lens aberration information into various process flows 有权将透镜像差信息合并到各种工艺流程中的方法公开(公告)号：US06880135B2
公开(公告)日：2005-04-12
申请号：US10005615
申请日：2001-11-07
CPC分类号： G03F7/705 , G03F7/70425 , G03F7/70533
摘要： A method of evaluating a stepper process affected by lens aberration is provided. The method includes receiving, from a facilitator responding to a request, a set of optical models including lens aberration information, wherein the lens aberration information is difficult to extract from the optical models. A decision can be made using the set of optical models. The decision could include determining which stepper(s) can be used (or should be avoided) with a mask, a layout, a process, and/or a chemistry. The decision could include ranking a plurality of steppers based on mask data to determine the best stepper (or next best steppers) to use.
摘要翻译： 提供了一种评估受镜头像差影响的步进过程的方法。 该方法包括从响应于请求的协调者接收包括透镜像差信息的一组光学模型，其中难以从光学模型中提取透镜像差信息。 可以使用该组光学模型进行决定。 该决定可以包括使用掩模，布局，过程和/或化学来确定可以使用（或应该避免）哪个步进器。 该决定可以包括基于掩模数据来排列多个步进器以确定要使用的最佳步进器（或下一个最佳步进器）。
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9.发明授权公开(公告)号：US08316326B1
公开(公告)日：2012-11-20
申请号：US12435246
申请日：2009-05-04
申请人： Christophe Pierrat
发明人： Christophe Pierrat
IPC分类号： G06F17/50
CPC分类号： G03F7/70125 , G03F1/70 , G03F7/70283 , G03F7/705
摘要： In accordance with some embodiments, a method is provided for creating a photolithographic component, comprising: determining a target pattern for a circuit layout, the target pattern comprising target features; identifying a set of periodic target features within the target pattern; calculating a relationship between feature and pitch for the set of periodic target features; and determining a mask pattern from the target pattern using the relationship, wherein the mask pattern has a set of periodic mask features configured to result in projection of a first subset of the set of periodic target features when exposed to a light source that induces a first phase effect, and configured to result in projection of a second subset of the set of periodic target features when exposed to a light source that induces a second phase effect. In further embodiments, the method outputs the mask pattern as a mask dataset.
摘要翻译： 根据一些实施例，提供了一种用于创建光刻部件的方法，包括：确定电路布局的目标图案，所述目标图案包括目标特征; 识别目标模式内的一组周期性目标特征; 计算一组周期性目标特征的特征和音调之间的关系; 以及使用所述关系从所述目标图案确定掩模图案，其中所述掩模图案具有一组周期性掩模特征，其被配置为当暴露于引起所述第一 并且被配置为当暴露于引起第二相位效应的光源时导致该组周期性目标特征的第二子集的投影。 在另外的实施例中，该方法输出掩模图案作为掩码数据集。
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公开(公告)号：US20110207056A1
公开(公告)日：2011-08-25
申请号：US13066816
申请日：2011-04-25
CPC分类号： B82Y10/00 , G03F7/70325 , G03F7/70958
摘要： Improvements in the fabrication of integrated circuits are driven by the decrease of the size of the features printed on the wafers. Current lithography techniques limits have been extended through the use of phase-shifting masks, off-axis illumination, and proximity effect correction. More recently, liquid immersion lithography has been proposed as a way to extend even further the limits of optical lithography. This invention described a methodology based on contact or proximity printing using a projection lens to define the image of the mask onto the wafer. As the imaging is performed in a solid material, larger refractive indices can be obtained and the resolution of the imaging system can be increased.
摘要翻译： 集成电路制造的改进由印刷在晶片上的特征的尺寸的减小驱动。 通过使用相移掩模，离轴照明和接近效应校正，目前的光刻技术限制已得到扩展。 最近，已经提出液浸光刻作为进一步扩展光学光刻的限制的一种方式。 本发明描述了一种基于使用投影透镜的接触或邻近打印以将掩模的图像定义到晶片上的方法。 当以固体材料进行成像时，可以获得更大的折射率并且可以提高成像系统的分辨率。
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