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    SYSTEM FOR MIGRATING STASH TRANSACTIONS
    1.
    发明申请
    SYSTEM FOR MIGRATING STASH TRANSACTIONS 有权
    移动交易系统

    公开(公告)号：US20160004654A1

    公开(公告)日：2016-01-07

    申请号：US14324233

    申请日：2014-07-06

    申请人： Yashpal Dutta ,  Himanshu Goel ,  Varun Sethi

    发明人： Yashpal Dutta ,  Himanshu Goel ,  Varun Sethi

    IPC分类号： G06F13/28 ,  G06F13/42

    CPC分类号： G06F13/28 ,  G06F3/00 ,  G06F9/466 ,  G06F9/4856 ,  G06F9/5088 ,  G06F12/00 ,  G06F12/1081 ,  G06F13/00 ,  G06F2212/1016

    摘要： A system for migrating stash transactions includes first and second cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output (I/O) device, a stash transaction migration management unit (STMMU), a queue manager and an operating system (OS) scheduler. The I/O device generates a first stash transaction request for a first data frame. The queue manager stores the first stash transaction request. When the first core executes a first thread, the queue manager stashes the first data frame to the first core by way of the IOMMU. The OS scheduler migrates the first thread from the first core to the second core and generates pre-empt notifiers. The STMMU uses the pre-empt notifiers to update the IOMMU mapping table and generate a stash replay command. The queue manager receives the stash replay command and stashes the first data frame to the second core.

    摘要翻译： 用于迁移存储交易的系统包括第一和第二内核，输入/输出存储器管理单元（IOMMU），IOMMU映射表，输入/输出（I / O）设备，存储交易迁移管理单元（STMMU）， 队列管理器和操作系统（OS）调度程序。 I / O设备为第一数据帧生成第一个存储交易请求。 队列管理器存储第一个隐藏事务请求。 当第一个核心执行第一个线程时，队列管理器通过IOMMU将第一个数据帧锁定到第一个内核。 OS调度程序将第一个线程从第一个内核迁移到第二个内核并生成预先通过的通知程序。 STMMU使用预先通过的通知程序来更新IOMMU映射表并生成一个存储重放命令。 队列管理器接收收件重播命令并将第一个数据帧封锁到第二个核心。

    System for migrating stash transactions
    2.
    发明授权
    System for migrating stash transactions 有权

    公开(公告)号：US09632958B2

    公开(公告)日：2017-04-25

    申请号：US14324233

    申请日：2014-07-06

    申请人： Yashpal Dutta ,  Himanshu Goel ,  Varun Sethi

    发明人： Yashpal Dutta ,  Himanshu Goel ,  Varun Sethi

    IPC分类号： G06F3/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/00

    CPC分类号： G06F13/28 ,  G06F3/00 ,  G06F9/466 ,  G06F9/4856 ,  G06F9/5088 ,  G06F12/00 ,  G06F12/1081 ,  G06F13/00 ,  G06F2212/1016

    摘要： A system for migrating stash transactions includes first and second cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output (I/O) device, a stash transaction migration management unit (STMMU), a queue manager and an operating system (OS) scheduler. The I/O device generates a first stash transaction request for a first data frame. The queue manager stores the first stash transaction request. When the first core executes a first thread, the queue manager stashes the first data frame to the first core by way of the IOMMU. The OS scheduler migrates the first thread from the first core to the second core and generates pre-empt notifiers. The STMMU uses the pre-empt notifiers to update the IOMMU mapping table and generate a stash replay command. The queue manager receives the stash replay command and stashes the first data frame to the second core.

    Clock distribution architecture for integrated circuit
    3.
    发明授权
    Clock distribution architecture for integrated circuit 有权
    集成电路的时钟分配架构

    公开(公告)号：US09148155B1

    公开(公告)日：2015-09-29

    申请号：US14248332

    申请日：2014-04-08

    申请人： Amit Aggarwal ,  Himanshu Goel ,  Ashish Malhotra ,  Ankit Pal

    发明人： Amit Aggarwal ,  Himanshu Goel ,  Ashish Malhotra ,  Ankit Pal

    IPC分类号： H03L7/08 ,  H03K3/017

    CPC分类号： H03L7/06 ,  G06F1/04

    摘要： An integrated circuit (IC) includes multiple circuit modules that have specific clocking requirements, multiple clock sources (e.g., PLLs, duty cycle re-shaper, etc.), and at least one clock input port. The clock sources have specific clock source specifications, and the circuit modules have specific clocking requirements. The clock sources are selected based on an identification of the most common clocking requirements, and then placed at routing distances measured from the input port that are less than corresponding predetermined maximum routing distances such that the clocking requirements of the circuit modules are met. The IC thus generates clock signals internally, rather than externally.

    摘要翻译： 集成电路（IC）包括具有特定时钟要求的多个电路模块，多个时钟源（例如，PLL，占空比重新整形器等）以及至少一个时钟输入端口。 时钟源具有特定的时钟源规格，电路模块具有特定的时钟要求。 基于最常见的时钟要求的识别来选择时钟源，然后将其从输入端口测量的路由距离设置为小于相应的预定最大路由距离，使得满足电路模块的时钟要求。 因此，IC在内部而不是外部产生时钟信号。

    CLOCK DISTRIBUTION ARCHITECTURE FOR INTEGRATED CIRCUIT
    4.
    发明申请
    CLOCK DISTRIBUTION ARCHITECTURE FOR INTEGRATED CIRCUIT 有权
    集成电路的时钟分配架构

    公开(公告)号：US20150288366A1

    公开(公告)日：2015-10-08

    申请号：US14248332

    申请日：2014-04-08

    申请人： Amit Aggarwal ,  Himanshu Goel ,  Ashish Malhotra ,  Ankit Pal

    发明人： Amit Aggarwal ,  Himanshu Goel ,  Ashish Malhotra ,  Ankit Pal

    IPC分类号： H03L7/08 ,  H03K3/017

    CPC分类号： H03L7/06 ,  G06F1/04

    摘要： An integrated circuit (IC) includes multiple circuit modules that have specific clocking requirements, multiple clock sources (e.g., PLLs, duty cycle re-shaper, etc.), and at least one clock input port. The clock sources have specific clock source specifications, and the circuit modules have specific clocking requirements. The clock sources are selected based on an identification of the most common clocking requirements, and then placed at routing distances measured from the input port that are less than corresponding predetermined maximum routing distances such that the clocking requirements of the circuit modules are met. The IC thus generates clock signals internally, rather than externally.

    摘要翻译： 集成电路（IC）包括具有特定时钟要求的多个电路模块，多个时钟源（例如，PLL，占空比重新整形器等）以及至少一个时钟输入端口。 时钟源具有特定的时钟源规格，电路模块具有特定的时钟要求。 基于最常见的时钟要求的识别来选择时钟源，然后将其从输入端口测量的路由距离设置为小于相应的预定最大路由距离，使得满足电路模块的时钟要求。 因此，IC在内部而不是外部产生时钟信号。

    METHOD AND SYSTEM FOR DESIGNING TEST CIRCUIT IN A SYSTEM ON CHIP
    5.
    发明申请
    METHOD AND SYSTEM FOR DESIGNING TEST CIRCUIT IN A SYSTEM ON CHIP 失效
    在芯片系统中设计测试电路的方法和系统

    公开(公告)号：US20080127021A1

    公开(公告)日：2008-05-29

    申请号：US11866965

    申请日：2007-10-03

    申请人： Himanshu Goel ,  Amit Sharma

    发明人： Himanshu Goel ,  Amit Sharma

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G01R31/318536

    摘要： A method and system for designing a test circuit in a System on Chip (SOC) includes identifying the test design constraints of the test circuit. The SOC is partitioned logically into a first set of logic blocks and a second set of logic blocks. A first set of scan chains is inserted in the first set of logic blocks, and a second set of scan chains is inserted in the second set of logic blocks, based on the test design constraints. Bypass circuits are inserted in the paths of the second set of scan chains, which are capable of bypassing at least one logic block of the second set of logic blocks during testing of the SOC.

    摘要翻译： 一种用于在片上系统（SOC）中设计测试电路的方法和系统包括识别测试电路的测试设计约束。 SOC被逻辑地分成第一组逻辑块和第二组逻辑块。 第一组扫描链被插入到第一组逻辑块中，并且基于测试设计约束将第二组扫描链插入到第二组逻辑块中。 旁路电路插入在第二组扫描链的路径中，其能够在测试SOC期间绕过第二组逻辑块的至少一个逻辑块。

    Low leakage current operation of integrated circuit using scan chain
    6.
    发明授权
    Low leakage current operation of integrated circuit using scan chain 有权
    使用扫描链的集成电路的低漏电流操作

    公开(公告)号：US08689068B2

    公开(公告)日：2014-04-01

    申请号：US13305702

    申请日：2011-11-28

    申请人： Siddhartha Jain ,  Himanshu Goel ,  Himanshu Kukreja

    发明人： Siddhartha Jain ,  Himanshu Goel ,  Himanshu Kukreja

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318555 ,  G01R31/318575

    摘要： An integrated circuit (IC) having a low leakage current mode of operation has a number of modules for running respective applications. The modules have respective cells and respective test scan chain elements. The IC also has a controller for configuring an active module to operate in a functional mode and a selected inactive module to operate in a low leakage current mode. Configuring the selected inactive module to operate in low leakage current mode includes enabling scan mode of the selected inactive module, and applying a low leakage vector of input signals from the controller to the cells of the inactive module using the scan chain. Functional data outputs of the inactive module are disabled during low leakage current mode. In the meantime, the active modules continue to operate in the functional mode.

    摘要翻译： 具有低泄漏电流操作模式的集成电路（IC）具有用于运行各种应用的多个模块。 模块具有各自的单元和相应的测试扫描链元件。 该IC还具有用于配置有源模块以在功能模式下操作的控制器和所选择的非活动模块以低泄漏电流模式操作。 将所选择的非活动模块配置为以低泄漏电流模式工作，包括启用所选非活动模块的扫描模式，以及使用扫描链将来自控制器的输入信号的低泄漏矢量应用于非活动模块的单元。 低电流模式下禁用模块的功能数据输出。 同时，主动模块继续在功能模式下运行。

    Method and system for designing test circuit in a system on chip
    7.
    发明授权
    Method and system for designing test circuit in a system on chip 失效
    在芯片系统中设计测试电路的方法和系统

    公开(公告)号：US07657854B2

    公开(公告)日：2010-02-02

    申请号：US11866965

    申请日：2007-10-03

    申请人： Himanshu Goel ,  Amit Sharma

    发明人： Himanshu Goel ,  Amit Sharma

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5045 ,  G01R31/318536

    摘要： A method and system for designing a test circuit in a System on Chip (SOC) includes identifying the test design constraints of the test circuit. The SOC is partitioned logically into a first set of logic blocks and a second set of logic blocks. A first set of scan chains is inserted in the first set of logic blocks, and a second set of scan chains is inserted in the second set of logic blocks, based on the test design constraints. Bypass circuits are inserted in the paths of the second set of scan chains, which are capable of bypassing at least one logic block of the second set of logic blocks during testing of the SOC.

    摘要翻译： 一种用于在片上系统（SOC）中设计测试电路的方法和系统包括识别测试电路的测试设计约束。 SOC被逻辑地分成第一组逻辑块和第二组逻辑块。 第一组扫描链被插入到第一组逻辑块中，并且基于测试设计约束将第二组扫描链插入到第二组逻辑块中。 旁路电路插入在第二组扫描链的路径中，其能够在测试SOC期间绕过第二组逻辑块的至少一个逻辑块。

    Resource management apparatus, systems, and methods
    8.
    发明申请
    Resource management apparatus, systems, and methods 审中-公开
    资源管理装置，系统和方法

    公开(公告)号：US20050144415A1

    公开(公告)日：2005-06-30

    申请号：US10750933

    申请日：2003-12-30

    申请人： Sachin Doshi ,  Himanshu Goel

    发明人： Sachin Doshi ,  Himanshu Goel

    IPC分类号： G06F9/50 ,  G06F13/00

    CPC分类号： G06F9/5016

    摘要： An apparatus and a system, as well as a method and article, may operate to allocate one or more links from a plurality of memory locations included in a memory segment of a memory to a port at substantially one time.

    摘要翻译： 设备和系统以及方法和物品可以操作以从基本上一次的存储器的存储器段中包括的多个存储器位置中分配一个或多个链路到端口。