摘要:
Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame maker and a predefined binary value in an output of the logic function.
摘要:
Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame maker and a predefined binary value in an output of the logic function.
摘要:
Operations of an electronic device are simulated by generating and executing a bit-accurate model of the device using an input signal having at least one transition that corresponds to a step input having a pre-transition value (e.g., 0 for a positive transition) for a specified duration before the transition and a post-transition value (e.g., 1 for a positive transition) for a specified duration after the transition. The corresponding step-response results are differentiated with respect to time to generate impulse-response results for the device. The impulse-response results are converted into the frequency domain to determine frequency-domain characteristics of the device that are used to generate a statistical model of the device, which can be executed to simulate all operations of the device, include low bit-error-rate (BER) simulations that would take too long to simulate using the bit-accurate model.
摘要:
In order to compensate for phase offset between different sets of circuitry having different synchronous clock domains, transmit (TX) circuitry of one domain is configured to transmit a pattern signal (e.g., a pseudo random bit sequence) to receive (RX) circuitry of the other domain. The RX circuitry cycles through a number of different phase-shifted RX clock signals to determine which selected clock signals result in valid RX pattern signals. The RX circuitry is then able to select one of the phase-shifted clock signals for use in normal processing of an RX data signal received from the TX circuitry.
摘要:
The present invention implements an apparatus for calibrating a phase locked loop (PLL) circuit. The apparatus includes a detector for detecting frequencies of a reference signal and a controlled oscillator contained in the PLL circuit. The detector outputs the frequency difference to a control circuit. The control circuit is programmed to adjust one or more control signals to the controlled oscillator based upon the frequency difference in an orderly fashion to complete the calibration process.
摘要:
In an exemplary embodiment, a data alignment system comprises a First-In First-Out register (FIFO), a programmable pattern generator connected to the FIFO, and a controller connected to the programmable pattern generator and the FIFO. The FIFO is configured to provide data to or receive data from a first data lane of a serial data link having one or more lanes. Each data lane of the serial data link is configured to transmit a respective serial data stream. The programmable pattern generator is configured to generate a plurality of alignment symbols. The controller is configured to manage the alignment of the one or more data lanes of the serial data link and the insertion of a selected one of the plurality of alignment symbols into each of the serial data streams.
摘要:
The present invention implements an apparatus for calibrating a phase locked loop (PLL) circuit. The apparatus includes a detector for detecting frequencies of a reference signal and a controlled oscillator contained in the PLL circuit. The detector outputs the frequency difference to a control circuit. The control circuit is programmed to adjust one or more control signals to the controlled oscillator based upon the frequency difference in an orderly fashion to complete the calibration process.
摘要:
In order to compensate for phase offset between different sets of circuitry having different synchronous clock domains, transmit (TX) circuitry of one domain is configured to transmit a pattern signal (e.g., a pseudo random bit sequence) to receive (RX) circuitry of the other domain. The RX circuitry cycles through a number of different phase-shifted RX clock signals to determine which selected clock signals result in valid RX pattern signals. The RX circuitry is then able to select one of the phase-shifted clock signals for use in normal processing of an RX data signal received from the TX circuitry.
摘要:
In an exemplary embodiment, a data alignment system comprises a First-In First-Out register (FIFO), a programmable pattern generator connected to the FIFO, and a controller connected to the programmable pattern generator and the FIFO. The FIFO is configured to provide data to or receive data from a first data lane of a serial data link having one or more lanes. Each data lane of the serial data link is configured to transmit a respective serial data stream. The programmable pattern generator is configured to generate a plurality of alignment symbols. The controller is configured to manage the alignment of the one or more data lanes of the serial data link and the insertion of a selected one of the plurality of alignment symbols into each of the serial data streams.
摘要:
Techniques are disclosed for asynchronous calibration for eye diagram generation. For example, a method for calibrating a process for generating a data eye associated with a received signal comprises the following steps. Samples of the received signal are obtained for a first unit interval using a first data latch and a roaming latch. A delay offset is determined between the first data latch and the roaming latch by comparing at least one sample obtained using the first data latch and at least one sample obtained using the roaming latch, wherein the delay offset determined by the comparison is used to calibrate the process for generating the data eye associated with the received signal. A similar comparison may be done for a second data latch and used to calibrate the process. The method is able to find the accurate position of each data latch with respect to the roaming latch so as to improve the accuracy of data decoding in a digital receiver, i.e., provide receiver optimization.