公开(公告)号：US08699550B2

公开(公告)日：2014-04-15

申请号：US13425467

申请日：2012-03-21

申请人： Yasser Ahmed ,  Xingdong Dai

发明人： Yasser Ahmed ,  Xingdong Dai

IPC分类号： H04B1/38 ,  H04L5/16

CPC分类号： H04L7/02 ,  H04L7/0337

摘要： In order to compensate for phase offset between different sets of circuitry having different synchronous clock domains, transmit (TX) circuitry of one domain is configured to transmit a pattern signal (e.g., a pseudo random bit sequence) to receive (RX) circuitry of the other domain. The RX circuitry cycles through a number of different phase-shifted RX clock signals to determine which selected clock signals result in valid RX pattern signals. The RX circuitry is then able to select one of the phase-shifted clock signals for use in normal processing of an RX data signal received from the TX circuitry.

摘要翻译： 为了补偿具有不同同步时钟域的不同电路组之间的相位偏移，一个域的发射（TX）电路被配置为发送模式信号（例如，伪随机位序列）以接收（RX）电路 其他域名 RX电路循环许多不同的相移RX时钟信号，以确定哪些选定的时钟信号产生有效的RX模式信号。 然后，RX电路能够选择一个相移时钟信号，以用于从TX电路接收的RX数据信号的正常处理。

公开(公告)号：US20090168862A1

公开(公告)日：2009-07-02

申请号：US11967463

申请日：2007-12-31

申请人： Yasser Ahmed ,  Xingdong Dai ,  Mohammad S. Mobin ,  Lane A. Smith

发明人： Yasser Ahmed ,  Xingdong Dai ,  Mohammad S. Mobin ,  Lane A. Smith

IPC分类号： H04L27/01

CPC分类号： H04L27/01 ,  H04L7/0066 ,  H04L7/0083 ,  H04L25/4904

摘要： Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame maker and a predefined binary value in an output of the logic function.

摘要翻译： 提供了用于检测和解码自适应均衡训练帧（具有包括二进制和二进制零序列的帧标记）的方法和装置。 通过移位接收到的数据来检测训练帧; 在移位的接收数据的一端插入至少一个二进制值以产生所接收数据的修改版本; 对所接收的数据应用逻辑功能以及当对应的位位置具有不同值时识别的接收数据的修改版本; 以及当所述逻辑功能的输出在第二二进制值的字符串的大致中间具有第一二进制值时，检测所述帧标记。 使用框架制造商的近似中心之间的距离和逻辑功能的输出中的预定二进制值对训练帧进行解码。

公开(公告)号：US20140025350A1

公开(公告)日：2014-01-23

申请号：US13553983

申请日：2012-07-20

申请人： Xingdong Dai ,  Yasser Ahmed

发明人： Xingdong Dai ,  Yasser Ahmed

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Operations of an electronic device are simulated by generating and executing a bit-accurate model of the device using an input signal having at least one transition that corresponds to a step input having a pre-transition value (e.g., 0 for a positive transition) for a specified duration before the transition and a post-transition value (e.g., 1 for a positive transition) for a specified duration after the transition. The corresponding step-response results are differentiated with respect to time to generate impulse-response results for the device. The impulse-response results are converted into the frequency domain to determine frequency-domain characteristics of the device that are used to generate a statistical model of the device, which can be executed to simulate all operations of the device, include low bit-error-rate (BER) simulations that would take too long to simulate using the bit-accurate model.

摘要翻译： 通过使用具有至少一个转换的输入信号来生成和执行装置的比特精确模型来模拟电子装置的操作，所述转换对应于具有预转换值的步进输入（例如，对于正转换为0），用于 转换前的指定持续时间和过渡后的指定持续时间后的转换后值（例如，1为正转移）。 相应的步进响应结果相对于时间被区分以产生该装置的脉冲响应结果。 脉冲响应结果被转换为频域以确定用于生成设备的统计模型的设备的频域特性，其可以被执行以模拟设备的所有操作，包括低位误差 - 速率（BER）模拟，需要太长时间来模拟使用位精确模型。

公开(公告)号：US20130251007A1

公开(公告)日：2013-09-26

申请号：US13425467

申请日：2012-03-21

申请人： Yasser Ahmed ,  Xingdong Dai

发明人： Yasser Ahmed ,  Xingdong Dai

IPC分类号： H04B1/38

CPC分类号： H04L7/02 ,  H04L7/0337

摘要： In order to compensate for phase offset between different sets of circuitry having different synchronous clock domains, transmit (TX) circuitry of one domain is configured to transmit a pattern signal (e.g., a pseudo random bit sequence) to receive (RX) circuitry of the other domain. The RX circuitry cycles through a number of different phase-shifted RX clock signals to determine which selected clock signals result in valid RX pattern signals. The RX circuitry is then able to select one of the phase-shifted clock signals for use in normal processing of an RX data signal received from the TX circuitry.

摘要翻译： 为了补偿具有不同同步时钟域的不同电路组之间的相位偏移，一个域的发射（TX）电路被配置为发送模式信号（例如，伪随机位序列）以接收（RX）电路 其他域名 RX电路循环许多不同的相移RX时钟信号，以确定哪些选定的时钟信号产生有效的RX模式信号。 然后，RX电路能够选择一个相移时钟信号，以用于从TX电路接收的RX数据信号的正常处理。

公开(公告)号：US08428195B2

公开(公告)日：2013-04-23

申请号：US11967463

申请日：2007-12-31

申请人： Yasser Ahmed ,  Xingdong Dai ,  Mohammad S. Mobin ,  Lane A. Smith

发明人： Yasser Ahmed ,  Xingdong Dai ,  Mohammad S. Mobin ,  Lane A. Smith

IPC分类号： H04L27/06

CPC分类号： H04L27/01 ,  H04L7/0066 ,  H04L7/0083 ,  H04L25/4904

摘要： Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame maker and a predefined binary value in an output of the logic function.

摘要翻译： 提供了用于检测和解码自适应均衡训练帧（具有包括二进制和二进制零序列的帧标记）的方法和装置。 通过移位接收到的数据来检测训练帧; 在移位的接收数据的一端插入至少一个二进制值以产生所接收数据的修改版本; 对所接收的数据应用逻辑功能以及当对应的位位置具有不同值时识别的接收数据的修改版本; 以及当所述逻辑功能的输出在第二二进制值的字符串的大致中间具有第一二进制值时，检测所述帧标记。 使用框架制造商的近似中心之间的距离和逻辑功能的输出中的预定二进制值对训练帧进行解码。

公开(公告)号：US07995695B2

公开(公告)日：2011-08-09

申请号：US11969440

申请日：2008-01-04

申请人： Yasser Ahmed ,  Xingdong Dai ,  Vladimir Sindalovsky ,  Lane Smith

发明人： Yasser Ahmed ,  Xingdong Dai ,  Vladimir Sindalovsky ,  Lane Smith

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： H03M9/00 ,  H04L7/005 ,  H04L7/04

摘要： In an exemplary embodiment, a data alignment system comprises a First-In First-Out register (FIFO), a programmable pattern generator connected to the FIFO, and a controller connected to the programmable pattern generator and the FIFO. The FIFO is configured to provide data to or receive data from a first data lane of a serial data link having one or more lanes. Each data lane of the serial data link is configured to transmit a respective serial data stream. The programmable pattern generator is configured to generate a plurality of alignment symbols. The controller is configured to manage the alignment of the one or more data lanes of the serial data link and the insertion of a selected one of the plurality of alignment symbols into each of the serial data streams.

摘要翻译： 在示例性实施例中，数据对准系统包括先进先出寄存器（FIFO），连接到FIFO的可编程模式发生器和连接到可编程模式发生器和FIFO的控制器。 FIFO被配置为向具有一个或多个通道的串行数据链路的第一数据通道提供数据或从其接收数据。 串行数据链路的每个数据通道被配置为发送相应的串行数据流。 可编程模式发生器被配置为生成多个对准符号。 控制器被配置为管理串行数据链路的一个或多个数据通道的对准以及将多个对准符号中选择的一个对准符号插入到每个串行数据流中。

公开(公告)号：US07714667B2

公开(公告)日：2010-05-11

申请号：US11934426

申请日：2007-11-02

申请人： Xingdong Dai ,  Yasser Ahmed ,  Christopher J. Abel ,  Shawn Michael Logan

发明人： Xingdong Dai ,  Yasser Ahmed ,  Christopher J. Abel ,  Shawn Michael Logan

IPC分类号： H03L7/113

CPC分类号： H03L7/18 ,  H03L7/087 ,  H03L7/095 ,  H03L2207/06

摘要： The present invention implements an apparatus for calibrating a phase locked loop (PLL) circuit. The apparatus includes a detector for detecting frequencies of a reference signal and a controlled oscillator contained in the PLL circuit. The detector outputs the frequency difference to a control circuit. The control circuit is programmed to adjust one or more control signals to the controlled oscillator based upon the frequency difference in an orderly fashion to complete the calibration process.

摘要翻译： 本发明实现了一种用于校准锁相环（PLL）电路的装置。 该装置包括用于检测PLL电路中包含的参考信号和受控振荡器的频率的检测器。 检测器将频差输出到控制电路。 控制电路被编程为基于有序的频率差来调整一个或多个控制信号到受控振荡器以完成校准过程。

公开(公告)号：US20090115536A1

公开(公告)日：2009-05-07

申请号：US11934426

申请日：2007-11-02

申请人： Xingdong Dai ,  Yasser Ahmed ,  Christopher J. Abel ,  Shawn Michael Logan

发明人： Xingdong Dai ,  Yasser Ahmed ,  Christopher J. Abel ,  Shawn Michael Logan

IPC分类号： H03L7/099 ,  G01R23/00

CPC分类号： H03L7/18 ,  H03L7/087 ,  H03L7/095 ,  H03L2207/06

摘要： The present invention implements an apparatus for calibrating a phase locked loop (PLL) circuit. The apparatus includes a detector for detecting frequencies of a reference signal and a controlled oscillator contained in the PLL circuit. The detector outputs the frequency difference to a control circuit. The control circuit is programmed to adjust one or more control signals to the controlled oscillator based upon the frequency difference in an orderly fashion to complete the calibration process.

摘要翻译： 本发明实现了一种用于校准锁相环（PLL）电路的装置。 该装置包括用于检测PLL电路中包含的参考信号和受控振荡器的频率的检测器。 检测器将频差输出到控制电路。 控制电路被编程为基于有序的频率差来调整一个或多个控制信号到受控振荡器以完成校准过程。

公开(公告)号：US07350002B2

公开(公告)日：2008-03-25

申请号：US11008745

申请日：2004-12-09

申请人： Yasser Ahmed

发明人： Yasser Ahmed

IPC分类号： G06F13/00

CPC分类号： G06F13/368

摘要： A low-latency, peer-to-peer TDM bus including one or more data lines and one or more control lines is provided. Attached devices access the bus sequentially in order of their bus addresses. During a device's access period, if the device has data to transmit, the device places its address on the data lines, asserts a START signal on the bus, and proceeds to transmit data to the other devices on the bus. When the data transmission is completed, the device asserts an END signal on the bus, thus passing control of the bus to the next device in the sequence. If the device has no data to transmit, the device simply places its address on the data lines, asserts the START signal, and asserts the END signal, and control passes directly to the next device in line. In this manner, each device has an opportunity to transmit on the bus.

摘要翻译： 提供了包括一个或多个数据线和一个或多个控制线的低等待时间的对等TDM总线。 连接的设备按照总线地址顺序访问总线。 在设备访问期间，如果设备具有要发送的数据，则设备将其地址放置在数据线上，在总线上断言START信号，并继续向总线上的其他设备发送数据。 当数据传输完成时，器件在总线上断言END信号，从而将总线的控制按顺序传送到下一个器件。 如果设备没有要发送的数据，则设备只需将其地址放置在数据线上，断言START信号，并断言END信号，并且控制直接传递到下一个设备。 以这种方式，每个设备都有机会在总线上传输。

公开(公告)号：US20080010552A1

公开(公告)日：2008-01-10

申请号：US11418401

申请日：2006-05-04

申请人： Yasser Ahmed ,  Robert Kapuschinsky ,  Ashok Khandelwal ,  Samuel Khoo ,  Lane Smith

发明人： Yasser Ahmed ,  Robert Kapuschinsky ,  Ashok Khandelwal ,  Samuel Khoo ,  Lane Smith

IPC分类号： G06F11/00

CPC分类号： G06F11/221

摘要： Disclosed is a system and method for testing a dual mode interface. The dual mode interface includes a first strobe circuit and a second strobe circuit configured to be operable during a first operational mode and inoperable during a second operational mode. The dual mode interface also includes a first data circuit and a second data circuit configured to be operable during the first operational mode and the second operational mode. The dual mode interface also includes a signal line connecting an output of the second strobe circuit with an input of the first strobe circuit and a switch element configured to activate said signal line in response to receipt of a test signal.

摘要翻译： 公开了用于测试双模式接口的系统和方法。 双模式接口包括第一选通电路和第二选通电路，其被配置为在第一操作模式期间可操作并且在第二操作模式期间不可操作。 双模式接口还包括第一数据电路和第二数据电路，其被配置为在第一操作模式和第二操作模式期间可操作。 双模式接口还包括将第二选通电路的输出与第一选通电路的输入连接的信号线和被配置为响应于接收到测试信号而激活所述信号线的开关元件。