公开(公告)号：US4757266A

公开(公告)日：1988-07-12

申请号：US896985

申请日：1986-08-15

申请人： Yasuharu Yoshida ,  Masato Tahara ,  Manabu Yagi ,  Toru Matsuura

发明人： Yasuharu Yoshida ,  Masato Tahara ,  Manabu Yagi ,  Toru Matsuura

IPC分类号： H04L27/38 ,  H03D3/18 ,  H03K9/10

CPC分类号： H04L27/38

摘要： In a demodulation system comprising a demodulator (22) which demodulates a quadrature amplitude modulated signal into first and second sets of output digital signals by the use of a reference carrier signal (CA), a specific phase control signal is produced in a transient state by discriminating a plurality of areas and a plurality of zones defined on a phase plane of the modulated signal. The areas are defined by dividing the phase plane by both a pair of quadrant reference axes and a pair of auxiliary reference axes phase shifted by .pi./4 (radians) relative to the quadrant decision axes. The zones are defined along and adjacent to the auxiliary reference axes. First and second detection signals (S.sub.1 and S.sub.2) are produced by a read-only memory (35) as results of discrimination of the areas and the zones, respectively. The specific phase control signal is switched to a normal phase control signal produced in a normal state in the known manner. Alternatively, the first and the second detection signals may be supplied to a transversal equalizer (21) for controlling imaginary part weighting control signals.

摘要翻译： 在包括通过使用参考载波信号（CA）将正交幅度调制信号解调为第一和第二组输出数字信号的解调器（22）的解调系统中，特定相位控制信号在过渡状态下由 鉴别在调制信号的相位平面上限定的多个区域和多个区域。 这些区域通过将相位平面除以一对象限参考轴和相对于象限决定轴相移相移π/ 4（弧度）的一对辅助参考轴来定义。 这些区域沿着辅助参考轴线并与其相邻。 第一和第二检测信号（S1和S2）分别由区域和区域的区分结果由只读存储器（35）产生。 特定相位控制信号以已知的方式切换到以正常状态产生的正常相位控制信号。 或者，第一和第二检测信号可以被提供给用于控制虚部加权控制信号的横向均衡器（21）。

公开(公告)号：US4620159A

公开(公告)日：1986-10-28

申请号：US769922

申请日：1985-08-27

申请人： Yasuharu Yoshida ,  Manabu Yagi

发明人： Yasuharu Yoshida ,  Manabu Yagi

IPC分类号： H04L27/38 ,  H04L7/033 ,  H04L27/22 ,  H04L27/34 ,  H03D3/18

CPC分类号： H04L7/0334

摘要： In a demodulation circuit, a timing synchronizing circuit generates a timing signal representing a sampling timing of an A/D converter and has a timing signal generator, a polarity identification circuit and a logic circuit. The timing signal generator is phase-controlled by a phase control signal and generates a timing signal. The polarity identification circuit identifies a polarity of a differential coefficient of the baseband signal at a sampling point of the A/D converter and generates a polarity identification signal. Upon logic processing, the logic circuit supplies to the timing signal generator the phase control signal representing a deviation of an actual sampling point of the baseband signal from an optimal sampling point. A carrier asynchronism detection circuit detects an asynchronism state of a carrier regenerating circuit and supplies to the timing synchronizing circuit a signal which changes its loop parameter.

摘要翻译： 在解调电路中，定时同步电路产生表示A / D转换器的采样定时的定时信号，并具有定时信号发生器，极性识别电路和逻辑电路。 定时信号发生器由相位控制信号进行相位控制，并产生定时信号。 极性识别电路识别A / D转换器的采样点处的基带信号的微分系数的极性，并生成极性识别信号。 在逻辑处理时，逻辑电路向定时信号发生器提供表示基带信号与最佳采样点的实际采样点的偏差的相位控制信号。 载波异步检测电路检测载波再生电路的异步状态，并向定时同步电路提供改变其环路参数的信号。

公开(公告)号：US4975927A

公开(公告)日：1990-12-04

申请号：US434750

申请日：1989-11-13

申请人： Yasuharu Yoshida

发明人： Yasuharu Yoshida

IPC分类号： H04L27/01 ,  H04B3/06 ,  H04L7/02 ,  H04L7/027 ,  H04L25/03

CPC分类号： H04L7/0058 ,  H04L25/03038

摘要： In a digital demodulator, a recovered baseband signal is sampled in response to a clock pulse supplied from a VCO and converted to a digital signal representing one of multilevels of the sampled signal. Real-axis and imaginary-axis transversal equalizers are provided. Each equalizer has a tapped delay line for receiving the digital signal, a plurality to tap weight multipliers connected respectively to taps of the tapped delay line, and an adder. The adder of the real-axis transversal equalizer sums all outputs of the tap weight multipliers except for the output of one which is connected to a tap adjacent to the center tap for producing a partially equalized signal, while the adder of the other equalizer sums all outputs of the tap weight multipliers for producing a fully equalized signal. Both of the equalized signals are summed by an adder and applied to a phase control circuit which derives from it a VCO control signal so that it corresponds to a tap-weight control signal applied to the multiplier whose output is excluded from being summed by the adder of the real-axis transversal equalizer. The output of the adder is summed with the excluded multiplier output and supplied to a tap weight controller which controls the multipliers of both transversal equalizers.

公开(公告)号：US4823361A

公开(公告)日：1989-04-18

申请号：US122970

申请日：1987-11-19

申请人： Yasuharu Yoshida

发明人： Yasuharu Yoshida

IPC分类号： H04L27/38 ,  H04B1/12

CPC分类号： H04L27/38

摘要： A 2.sup.n -level demodulated signal is resolved into 2.sup.(n+m) equal intervals by an (n+m)-bit A/D converter (12) and an (n+m)th significant bit is produced from the LSB output of the converter as a representation of an interfering signal contained in the demodulated signal, where m is equal to or greater than unity. A subtractor (5p, 5q; 32p, 32q) cancels the interfering signal with a cancelling signal supplied from a feedback control circuit (9, 11, 7; 16-19; 30-31) which derives it by controlling the amplitude of the (n+m)th significant bit in accordance with the amount of the interfering signal still present in the output of the subtractor.

摘要翻译： 通过（n + m）位A / D转换器（12）将2n电平解调信号解析为2（n + m）个等间隔，并且从（n + m）位A / D转换器 转换器作为包含在解调信号中的干扰信号的表示，其中m等于或大于1。 减法器（5p，5q; 32p，32q）利用从反馈控制电路（9,11,7; 16-19; 30-31）提供的抵消信号来抵消干扰信号，该反馈控制电路通过控制（ 根据减法器的输出中仍然存在的干扰信号的量，n + m）个有效位。

公开(公告)号：US4703282A

公开(公告)日：1987-10-27

申请号：US878746

申请日：1986-06-26

申请人： Yasuharu Yoshida

发明人： Yasuharu Yoshida

IPC分类号： H04L25/06 ,  H04L27/01 ,  H04L27/08 ,  H04L27/38 ,  H03D3/18

CPC分类号： H04L27/01 ,  H04L25/064 ,  H04L25/066 ,  H04L27/08 ,  H04L27/3809

摘要： An AGC circuit for controlling an input level of a multi-level discriminator to an optimum one and a transversal equalizer capable of fully exhibiting an equalizing function thereof, each being installed in a digital demodulation system applicable to a multi-level communication system. The AGC circuit eliminates false pull-in to promote stable pull-in operations and is applicable not only to baseband signals having two or more levels but also to a 16 QAM system in microwave digital communication. Even when a demodulator is in an asynchronous state and input signals have significant intersymbol interference, the demodulation system is capable of being restored to normal to allow the equalizer to fully exhibit its capability.

摘要翻译： 一种用于将多电平鉴别器的输入电平控制为最佳的AGC电路，以及能够充分发挥其均衡功能的横向均衡器，每个都被安装在适用于多电平通信系统的数字解调系统中。 AGC电路消除了假引入以促进稳定的拉入操作，并且不仅适用于具有两个或多个电平的基带信号，而且还适用于微波数字通信中的16QAM系统。 即使当解调器处于异步状态并且输入信号具有明显的符号间干扰时，解调系统也能恢复正常以允许均衡器充分发挥其能力。

公开(公告)号：US08761003B2

公开(公告)日：2014-06-24

申请号：US10445963

申请日：2003-05-28

申请人： Yasuharu Yoshida

发明人： Yasuharu Yoshida

IPC分类号： H04J3/14

CPC分类号： H04L1/22

摘要： A transmission capacity of a transmitter is controlled by a signal input from a receiver through a propagation path. The receiver produces a control signal for controlling a system at the optimum transmission capacity which is obtained from monitored information such as transmission quality or reception C/N and the like, and outputs the control signal to the transmitter and a judging circuit. The judging circuit compares the transmission capacity of each line. When the transmission capacity of a first regular line is the lowest transmission capacity, a switching signal is output from the judging circuit. Then a transmission switching device and a reception switching device operate and the input signal on the first regular line is output through the spare line. The transmission capacity of the signal is that of the spare line.

摘要翻译： 发射机的传输容量由接收机通过传播路径输入的信号控制。 接收机产生用于控制系统的控制信号，该控制信号以从发送质量或接收C / N等等监视信息获得的最佳传输容量进行控制，并将控制信号输出到发射机和判断电路。 判断电路比较每行的传输容量。 当第一规则行的传输容量是最低传输容量时，从判断电路输出切换信号。 然后，传输切换装置和接收切换装置工作，并且通过备用线路输出第一常规线路上的输入信号。 信号的传输容量是备用线路的传输容量。

公开(公告)号：US06285858B1

公开(公告)日：2001-09-04

申请号：US09187742

申请日：1998-11-09

申请人： Yasuharu Yoshida

发明人： Yasuharu Yoshida

IPC分类号： H04B500

CPC分类号： G08G1/096783 ,  G07B15/063 ,  G08G1/096716 ,  G08G1/096758

摘要： A system for establishing radio communications between an in-vehicle unit and a road unit, including a signal controller in response to an output of an approaching vehicle detector, includes an on-board antenna forming part of the in-vehicle unit and provided to have directivity toward a road surface, a plurality of stationary devices, which form part of the road unit, provided in series between the signal controller and a terminator, and respectively coupled to the plurality of stationary antennas, and a plurality of stationary devices forming part of the road unit and provided in series between the signal controller and a terminator, and respectively coupled to the plurality of stationary antennas. Each of the plurality of stationary devices branches a signal transmitted thereto from the signal controller and applies the signal to the corresponding stationary antenna, and applies a signal transmitted thereto from the on-board antenna to the signal controller.

摘要翻译： 一种用于在车载单元和道路单元之间建立无线电通信的系统，包括响应于接近的车辆检测器的输出的信号控制器，包括形成车载单元的一部分并被提供以具有 构成道路单元的一部分的多个静止装置，串联连接在信号控制器和终端器之间，分别耦合到多个固定天线，以及多个固定装置，其形成一部分 所述道路单元并串联提供在所述信号控制器和终端器之间，并分别耦合到所述多个固定天线。 多个固定装置中的每一个分支从信号控制器传送到其的信号，并将信号施加到对应的固定天线，并且将从车载天线发送到其的信号施加到信号控制器。

公开(公告)号：US4553102A

公开(公告)日：1985-11-12

申请号：US633315

申请日：1984-07-23

申请人： Yasuharu Yoshida

发明人： Yasuharu Yoshida

IPC分类号： H04L25/06 ,  H04L27/38 ,  H03D1/06

CPC分类号： H04L25/067 ,  H04L27/3809

摘要： Multilevel baseband signals are applied to a full-wave rectifying section which produces first and second outputs. These outputs are applied to an analog-to-digital converting means which produces a plurality of recovered binary digital signals and an error signal. A controller is supplied with at least one recovered binary digital signal and the error signal, and produces two control signals which are fed to the full-wave rectifying section to compensate (a) first DC-drifts superimposed on the multilevel baseband signal and (b) second DC-drifts generated within the full-wave rectifying section itself.

摘要翻译： 多级基带信号被施加到产生第一和第二输出的全波整流部分。 这些输出被应用于产生多个恢复的二进制数字信号和误差信号的模拟 - 数字转换装置。 向控制器提供至少一个恢复的二进制数字信号和误差信号，并且产生两个控制信号，其被馈送到全波整流部分以补偿（a）叠加在多电平基带信号上的第一直流漂移和（b ）在全波整流部分本身内产生的第二直流漂移。

公开(公告)号：US4528512A

公开(公告)日：1985-07-09

申请号：US585653

申请日：1984-03-02

申请人： Yasuharu Yoshida

发明人： Yasuharu Yoshida

IPC分类号： H04L25/40 ,  H04L7/00 ,  H04L7/033 ,  H04L27/22 ,  H03L7/08

CPC分类号： H04L7/0334 ,  H04L7/0335

摘要： In a timing synchronizing circuit wherein a timing signal is regenerated from a baseband signal subjected to a bandwidth limitation, there are provided a voltage controlled oscillator whose oscillation frequency varies in accordance with a control signal, an A/D converter which samples and shapes the baseband signal by utilizing the output of the voltage controlled oscillator, a decision circuit for deciding the polarity of a differential coefficient of the baseband signal at an optimum sampling point on the basis of an output of the A/D converter, and a logic circuit responsive to the output of the decision circuit to apply a logical operation to a decision signal derived from the A/D converter and which decides whether or not the baseband signal shifts from a level corresponding to the optimum sampling point, thereby producing the control signal for the voltage controlled oscillator. According to this circuit the regenerated timing signal contains only a negligible amount of jitter components and always maintains an optimum timing without using any phase adjustment.

摘要翻译： 在定时信号从经受带宽限制的基带信号再生的定时同步电路中，提供了其振荡频率根据控制信号而变化的压控振荡器，A / D转换器对基带 信号通过利用压控振荡器的输出，判定电路，用于根据A / D转换器的输出，确定最佳采样点处的基带信号的微分系数的极性，以及响应于 判定电路的输出，对从A / D转换器得到的判定信号进行逻辑运算，判定基准信号是否偏离与最佳采样点对应的电平，由此产生电压的控制信号 受控振荡器。 根据该电路，再生的定时信号仅包含可忽略的抖动分量，并且始终保持最佳定时而不使用任何相位调整。

公开(公告)号：US4109102A

公开(公告)日：1978-08-22

申请号：US743910

申请日：1976-11-22

申请人： Yasuharu Yoshida ,  Yoshimi Tagashira

发明人： Yasuharu Yoshida ,  Yoshimi Tagashira

IPC分类号： H04L27/227 ,  H04L7/00

CPC分类号： H04L27/2273

摘要： A phase synchronizing circuit for processing a 2.sup.n- phase phase modulated input signal wherein the signal is detected by phase detectors each of whose outputs are then phase shifted through a phase angle determined by the ratio of a:b = 1:tan (.pi./2.sup.n+1) where a represents the amplitude of the phase detector output and b represents the amplitude of a signal orthogonal to the signal a. The 2.sup.n phase shifted signals repetitively undergo frequency doubling and then a combined signal from each pair of doublers is generated to successively reduce the signals to 2.sup.n-1 in number, then 2.sup.n-2 in number, and so forth, until only one pair of signals remains. A difference signal of the pair of signals is formed, which difference signal represents an error signal and is employed to operate a voltage controlled oscillator serving as the signal to be compared at each phase detector with the input signal, after undergoing an appropriate phase shift.The phase shift of each phase detector output signal is accomplished by attenuating the output signal of that one of the remaining phase detectors which is orthogonal with the output signal undergoing phase shift wherein the respective ratios of the amplitudes of the signals are 1:tan (.pi./2.sup.n+1). The output signal being phase shifted and the attenuated output signal being used to control the magnitude of the phase shift are combined in an adder (or subtractor) circuit to effect the phase shift.