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公开(公告)号：US4583225A
公开(公告)日：1986-04-15
申请号：US541402
申请日：1983-10-13
CPC分类号： H03M13/15
摘要： A Reed-Solomon code generator applicable to a digital signal recording/playback apparatus checks or corrects code errors in digital signals. The code generator eliminates the need for costly read only memory devices (ROM tables) and uses inexpensive registers, modulo 2 adders and multipliers instead.
摘要翻译： 适用于数字信号记录/重放装置的里德 - 所罗门码发生器检查或纠正数字信号中的码错误。 代码生成器不需要昂贵的只读存储器件（ROM表），并且使用廉价的寄存器，模2加法器和乘法器。
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公开(公告)号：US4416010A
公开(公告)日：1983-11-15
申请号：US254053
申请日：1981-04-14
CPC分类号： G11B20/1809
摘要： A double error correcting system is used in a digital signal reproducing apparatus, which is capable of correcting errors in two information vectors (information words) among a plurality of information vectors within one block by use of elements in a small number of correcting matrices and by using a memory device having a small memory capacity. A register is not required for temporarily storing the operational result obtained half-way between a plurality of performed operations. Instead, corrected information vectors are obtained from a memory circuit.
摘要翻译： 一种双重纠错系统被用在数字信号再现装置中，该装置能够通过使用少量的校正矩阵中的元素和通过使用少量校正矩阵中的元素来校正一个块内的多个信息向量中的两个信息向量（信息字）中的错误 使用具有小存储容量的存储器件。 不需要寄存器来临时存储在多个执行操作之间中途获得的操作结果。 相反，从存储器电路获得校正的信息向量。
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3.发明授权System for defeating erroneous correction in a digital signal reproducing apparatus 失效用于在数字信号再现装置中消除错误校正的系统
公开(公告)号：US4445216A
公开(公告)日：1984-04-24
申请号：US242293
申请日：1981-03-10
CPC分类号： G11B20/1809
摘要： A system for defeating erroneous correction in a digital signal reproducing apparatus. The system includes a reproducing circuit for reproducing a signal sequence in which information words and error correcting words are interleaved. A memory stores the reproduced digital signal sequence and produces a digital signal sequence made up of the information words and error correcting words, which are then de-interleaved and arranged in an original sequence. A correcting circuit corrects adjacent errors with respect to the digital signal sequence produced from the memory. A digital-to-analog converter converts a digital information signal obtained from the correcting circuit into an original analog information signal. The correcting circuit calculates partial syndromes according to predetermined equations and detects the number of erroneous words in one block which is made up of interleaved words. The error correcting operation is stopped when there are certain set of conditions which are related to the values of the partial syndromes and when the number of erroneous words are satisfied. The system continues to stop the correcting operation until other sets of conditions are satisfied, in order to correct errors of up to two words in each of the blocks made up of the de-interleaved words.
摘要翻译： 一种用于消除数字信号再现装置中的错误校正的系统。 该系统包括用于再现其中信息字和纠错字被交错的信号序列的再现电路。 存储器存储再现的数字信号序列，并产生由信息字和纠错字组成的数字信号序列，然后以原始顺序进行解交织和排列。 校正电路相对于从存储器产生的数字信号序列校正相邻误差。 数模转换器将从校正电路获得的数字信息信号转换为原始模拟信息信号。 校正电路根据预定的方程式计算部分校正子，并检测由交错字组成的一个块中的错误字数。 当存在与部分综合征的值相关的某些条件集合以及满足错误字数时，停止纠错操作。 系统继续停止校正操作，直到满足其他条件为止，以便校正由解交错字组成的每个块中最多两个字的错误。
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公开(公告)号：US4333160A
公开(公告)日：1982-06-01
申请号：US95553
申请日：1979-11-19
CPC分类号： G11B20/1809
摘要： A memory control system comprises a first memory supplied with an incoming modulated digital signal which is formed by subjecting an analog signal to digital signal processing of discontinuous level modulation system, and a first control circuit for supplying a control signal to the first memory. The first control circuit producing the control signal for controlling the first memory in such a manner that the total memory capacity of the first memory is partitioned into a plurality (k) of memory capacity segments having given capacity values (lengths) for use, and the modulated digital signal is written in and further the modulated digital signal thus written in is read out with the order thereof rearranged, interrelatedly with the circulation of addresses through the plurality of divided memory capacity segments while maintaining constant the relationship in terms of capacity values (lengths) between the plurality of divided memory capacity segments.
摘要翻译： 存储器控制系统包括：第一存储器，其被提供有通过对模拟信号进行不连续电平调制系统的数字信号处理而形成的输入调制数字信号;以及第一控制电路，用于向第一存储器提供控制信号。 第一控制电路产生用于控制第一存储器的控制信号，使得第一存储器的总存储器容量被划分为具有给定容量值（长度）的多个（k）个存储容量段，并且 被调制的数字信号被写入，并且进一步地读出这样写入的调制数字信号，其顺序被重新排列，与通过多个划分的存储器容量段的地址的循环相关联，同时保持在容量值（长度）上的恒定关系 ）在多个划分的存储器容量段之间。
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公开(公告)号：US4420775A
公开(公告)日：1983-12-13
申请号：US305779
申请日：1981-09-25
申请人： Shigeru Yamazaki , Takao Arai , Masaharu Kobayashi , Takashi Hoshino , Chitoshi Hibino , Harukuni Kobari
发明人： Shigeru Yamazaki , Takao Arai , Masaharu Kobayashi , Takashi Hoshino , Chitoshi Hibino , Harukuni Kobari
摘要： A circuit for protecting a horizontal synchronous signal comprises a horizontal synchronous signal detecting circuit responsive to horizontal synchronous pulses included in a composite synchronous signal of a reproduced PCM signal, first and second horizontal synchronous pulse supplementing or adding circuits and an output switching circuit. The output switching circuit operates so that the first supplementing circuit delivers a first supplementary pulse in the absence of a single pulse of the original horizontal synchronous signal, and the second supplementing circuit produces one or more second supplementary pulses in the absence of a plurality of continuous pulses of the original horizontal synchronous signal. When the circuit returns to a condition in which produced horizontal synchronous pulses are synchronous with the original horizontal synchronous pulses, the time interval between adjacent pulses of the original pulses is detected to see whether the interval is either longer or shorter than a predetermined value. As a result, when a pulse first appeared after the returning point is within the predetermined interval, that pulse is removed so that the number of output horizontal synchronous pulses is correct.
摘要翻译： 用于保护水平同步信号的电路包括水平同步信号检测电路，其响应包括在再现的PCM信号的复合同步信号中的水平同步脉冲，第一和第二水平同步脉冲补充或加法电路以及输出切换电路。 输出切换电路操作，使得第一补充电路在没有原始水平同步信号的单个脉冲的情况下传送第一辅助脉冲，并且第二补充电路在没有多个连续的情况下产生一个或多个第二辅助脉冲 原始水平同步信号的脉冲。 当电路返回到产生的水平同步脉冲与原始水平同步脉冲同步的状态时，检测原始脉冲的相邻脉冲之间的时间间隔，以查看间隔是否比预定值更长或更短。 结果，当在返回点之后首先出现脉冲在预定间隔内时，该脉冲被去除，使得输出水平同步脉冲的数量是正确的。
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公开(公告)号：US4408326A
公开(公告)日：1983-10-04
申请号：US305375
申请日：1981-09-24
申请人： Takashi Takeuchi , Harukuni Kobari
发明人： Takashi Takeuchi , Harukuni Kobari
CPC分类号： H03M13/09 , G11B20/1809
摘要： An error correcting circuit particularly for an audio equipment makes use of the so-called adjacent code correction technology and an error pointer generated by the error detection code (CRCC). The circuit comprises a counter starting to count clock pulses in response to an operation start signal, a timing signal generator for steps of correction operation, a correction operation circuit operative with the timing signal, a storage circuit for storing operation results of the correction operation circuit, a monitoring circuit for monitoring the degree of execution of the correction operation steps in the correction operation circuit, using the output of the counter and a control circuit for controlling the storage of the operation results in the storage circuit, depending upon the output of the monitoring circuit.
摘要翻译： 专门用于音频设备的纠错电路利用所谓的相邻码校正技术和由错误检测码（CRCC）产生的错误指针。 电路包括响应于操作开始信号开始计数时钟脉冲的计数器，用于校正操作步骤的定时信号发生器，与定时信号一起操作的校正操作电路，用于存储校正操作电路的操作结果的存储电路 监视电路，用于使用计数器的输出和用于控制存储电路中的运算结果的存储的控制电路来监视校正操作电路中的校正操作步骤的执行程度，这取决于 监控电路。
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公开(公告)号：US08224161B2
公开(公告)日：2012-07-17
申请号：US11902654
申请日：2007-09-24
IPC分类号： H04N5/917
CPC分类号： G11B27/036 , G11B27/034 , G11B27/3027 , G11B27/329 , G11B2220/2562 , H04N9/8042
摘要： An audio signal is compressively encoded into encoding-resultant audio data. A video signal is compressively encoded into encoding-resultant video data. An audio time stamp for audio-vide synchronous reproduction is added to every unit of the encoding-resultant audio data. A video time stamp for audio-video synchronous reproduction is added to every unit of the encoding-resultant video data. The time-stamp-added audio data and the time-stamp-added video data are multiplexed into main data. To a plurality of first after-recording-purpose data for at least one of (1) the encoding-resultant audio data and (2) the encoding-resultant video data which form the main data, time stamps for reproduction synchronous with a portion of the main data and identification information for identifying the plurality of first after-recording-purpose data are added to convert the first after-recording-purpose data into second after-recording-purpose data. The second after-recording-purpose data are made into bit streams without being multiplexed with the main data.
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公开(公告)号：US20090028516A1
公开(公告)日：2009-01-29
申请号：US11902654
申请日：2007-09-24
CPC分类号： G11B27/036 , G11B27/034 , G11B27/3027 , G11B27/329 , G11B2220/2562 , H04N9/8042
摘要： An audio signal is compressively encoded into encoding-resultant audio data. A video signal is compressively encoded into encoding-resultant video data. An audio time stamp for audio-vide synchronous reproduction is added to every unit of the encoding-resultant audio data. A video time stamp for audio-video synchronous reproduction is added to every unit of the encoding-resultant video data. The time-stamp-added audio data and the time-stamp-added video data are multiplexed into main data. To a plurality of first after-recording-purpose data for at least one of (1) the encoding-resultant audio data and (2) the encoding-resultant video data which form the main data, time stamps for reproduction synchronous with a portion of the main data and identification information for identifying the plurality of first after-recording-purpose data are added to convert the first after-recording-purpose data into second after-recording-purpose data. The second after-recording-purpose data are made into bit streams without being multiplexed with the main data.
摘要翻译： 音频信号被压缩编码成编码结果音频数据。 视频信号被压缩编码成编码结果视频数据。 用于音频视频同步再现的音频时间戳被添加到编码结果音频数据的每个单元。 用于音频 - 视频同步再现的视频时间戳被添加到编码结果视频数据的每个单元。 添加了时间戳的音频数据和添加了时间戳的视频数据被复用到主数据中。 对于（1）编码结果音频数据和（2）形成主数据的编码结果视频数据中的至少一个的多个第一后记录用数据，再现同步的时间戳与一部分 添加用于识别多个第一再记录用途数据的主数据和识别信息，以将第一再记录用数据转换成第二再记录用数据。 第二记录后数据被制成比特流而不与主数据进行复用。
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公开(公告)号：US07289718B2
公开(公告)日：2007-10-30
申请号：US10244475
申请日：2002-09-17
CPC分类号： G11B27/036 , G11B27/034 , G11B27/3027 , G11B27/329 , G11B2220/2562 , H04N9/8042
摘要： An audio signal is compressively encoded into encoding-resultant audio data. A video signal is compressively encoded into encoding-resultant video data. An audio time stamp for audio-vide synchronous reproduction is added to every unit of the encoding-resultant audio data. A video time stamp for audio-video synchronous reproduction is added to every unit of the encoding-resultant video data. The time-stamp-added audio data and the time-stamp-added video data are multiplexed into main data. To a plurality of first after-recording-purpose data for at least one of (1) the encoding-resultant audio data and (2) the encoding-resultant video data which form the main data, time stamps for reproduction synchronous with a portion of the main data and identification information for identifying the plurality of first after-recording-purpose data are added to convert the first after-recording-purpose data into second after-recording-purpose data. The second after-recording-purpose data are made into bit streams without being multiplexed with the main data.
摘要翻译： 音频信号被压缩编码成编码结果音频数据。 视频信号被压缩编码成编码结果视频数据。 用于音频视频同步再现的音频时间戳被添加到编码结果音频数据的每个单元。 用于音频 - 视频同步再现的视频时间戳被添加到编码结果视频数据的每个单元。 添加了时间戳的音频数据和添加了时间戳的视频数据被复用到主数据中。 对于（1）编码结果音频数据和（2）形成主数据的编码结果视频数据中的至少一个的多个第一后记录用数据，再现同步的时间戳与一部分 添加用于识别多个第一再记录用途数据的主数据和识别信息，以将第一再记录用数据转换成第二再记录用数据。 第二记录后数据被制成比特流而不与主数据进行复用。
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公开(公告)号：US4020291A
公开(公告)日：1977-04-26
申请号：US606228
申请日：1975-08-20
摘要： A system for time compression and expansion of audio signals comprises a filter for filtering the fundamental frequency component of an input signal reproduced at a speed differing from that at the time of recording, first and second memory devices for carrying out writing in or memorizing and reading out at speeds in accordance with the frequency of applied clock pulses, a control signal forming circuit for forming gate control signals and clock pulse signals of different frequency from the output fundamental frequency component of the filter in synchronism with the pitch period thereof, and gates controlled by the gate control signals to pass or not pass the output signals of the first and second memory devices. A time compressed or expanded signal synchronized with the pitch period of the fundamental frequency component of the input signal is led out through these gates.
摘要翻译： 用于音频信号的时间压缩和扩展的系统包括用于对以与记录时不同的速度再现的输入信号的基频分量进行滤波的滤波器，用于执行写入或记忆和读取的第一和第二存储器件 根据施加的时钟脉冲的频率以速度输出;控制信号形成电路，用于与滤波器的输出基频分量同步地与其音调周期同步地形成门控制信号和不同频率的时钟脉冲信号，门控制 门控制信号通过或不通过第一和第二存储器件的输出信号。 与输入信号的基频分量的音调周期同步的时间压缩或扩展信号通过这些门引出。
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