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    Cache memory employing dynamically controlled data array start timing and a microprocessor using the same
    2.
    发明授权
    Cache memory employing dynamically controlled data array start timing and a microprocessor using the same 失效
    使用动态控制的数据阵列启动定时的高速缓存存储器和使用其的微处理器

    公开(公告)号：US06389523B1

    公开(公告)日：2002-05-14

    申请号：US09557220

    申请日：2000-04-25

    申请人： Yasuhisa Shimazaki ,  Seiichi Nagata ,  Katuhiro Norisue ,  Koichiro Ishibashi ,  Junichi Nishimoto ,  Shinichi Yoshioka ,  Susumu Narita

    发明人： Yasuhisa Shimazaki ,  Seiichi Nagata ,  Katuhiro Norisue ,  Koichiro Ishibashi ,  Junichi Nishimoto ,  Shinichi Yoshioka ,  Susumu Narita

    IPC分类号： G06F1206

    CPC分类号： G06F12/0864 ,  G06F2212/1028 ,  Y02D10/13

    摘要： A comparator is constituted such that a hit signal &phgr;hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.

    摘要翻译： 构成一个比较器，使命中信号phihit是高的，在地址阵列的每个方式建立命中检查之前，并且当已经建立了一个错误时，命中信号变低。 当时钟频率相对较高时，地址阵列由第一时钟信号激活，此后，在地址阵列中的命中检查建立之前，数据阵列的所有方式都被第二时钟信号激活。 当命中检查已经建立时，从命中的数据阵列中读取的数据被立即输出到数据线上，并以停止的方式进行操作。 这种新颖的结构实现了高速缓存操作。 当时钟频率相对较低时，在命中检查完成之后仅激活已经命中的数据阵列中的一种方式，从而降低了低速操作时的功耗。

    Cache memory employing dynamically controlled data array start timing and a microcomputer using the same
    3.
    发明授权
    Cache memory employing dynamically controlled data array start timing and a microcomputer using the same 失效
    使用动态控制的数据阵列启动定时的高速缓冲存储器和使用其的微型计算机

    公开(公告)号：US5860127A

    公开(公告)日：1999-01-12

    申请号：US653278

    申请日：1996-05-24

    申请人： Yasuhisa Shimazaki ,  Seiichi Nagata ,  Katuhiro Norisue ,  Koichiro Ishibashi ,  Junichi Nishimoto ,  Shinichi Yoshioka ,  Susumu Narita

    发明人： Yasuhisa Shimazaki ,  Seiichi Nagata ,  Katuhiro Norisue ,  Koichiro Ishibashi ,  Junichi Nishimoto ,  Shinichi Yoshioka ,  Susumu Narita

    IPC分类号： G06F12/00 ,  G06F12/06 ,  G06F12/08

    CPC分类号： G06F12/0864 ,  G06F2212/1028 ,  Y02B60/1225

    摘要： A comparator is constituted such that a hit signal .phi.hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.

    摘要翻译： 构成比较器，使得命中信号phi命中为高，在地址阵列的每个方式建立命中检查之前，并且当已经建立了一个虚构时，命中信号变低。 当时钟频率相对较高时，地址阵列由第一时钟信号激活，此后，在地址阵列中的命中检查建立之前，数据阵列的所有方式都被第二时钟信号激活。 当命中检查已经建立时，从命中的数据阵列中读取的数据被立即输出到数据线上，并以停止的方式进行操作。 这种新颖的结构实现了高速缓存操作。 当时钟频率相对较低时，在命中检查完成之后仅激活已经命中的数据阵列中的一种方式，从而降低了低速操作时的功耗。

    Cacche memory employing dynamically controlled data array start timing and a microcomputer using the same
    4.
    发明授权
    Cacche memory employing dynamically controlled data array start timing and a microcomputer using the same 失效
    采用动态控制的数据阵列启动定时的Cacche存储器和使用它的微型计算机

    公开(公告)号：US6070234A

    公开(公告)日：2000-05-30

    申请号：US118892

    申请日：1998-07-20

    申请人： Yasuhisa Shimazaki ,  Seiichi Nagata ,  Katuhiro Norisue ,  Koichiro Ishibashi ,  Junichi Nishimoto ,  Shinichi Yoshioka ,  Susumu Narita

    发明人： Yasuhisa Shimazaki ,  Seiichi Nagata ,  Katuhiro Norisue ,  Koichiro Ishibashi ,  Junichi Nishimoto ,  Shinichi Yoshioka ,  Susumu Narita

    IPC分类号： G06F12/00 ,  G06F12/06 ,  G06F12/08

    CPC分类号： G06F12/0864 ,  G06F2212/1028 ,  Y02B60/1225

    摘要： A comparator is constituted such that a hit signal .phi.hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.

    摘要翻译： 构成比较器，使得命中信号phi命中为高，在地址阵列的每个方式建立命中检查之前，并且当已经建立了一个虚构时，命中信号变低。 当时钟频率相对较高时，地址阵列由第一时钟信号激活，此后，在地址阵列中的命中检查建立之前，数据阵列的所有方式都被第二时钟信号激活。 当命中检查已经建立时，从命中的数据阵列中读取的数据被立即输出到数据线上，并以停止的方式进行操作。 这种新颖的结构实现了高速缓存操作。 当时钟频率相对较低时，在命中检查完成之后仅激活已经命中的数据阵列中的一种方式，从而降低了低速操作时的功耗。

    Translation lookaside buffer supporting multiple page sizes
    5.
    发明授权
    Translation lookaside buffer supporting multiple page sizes 失效
    支持多页尺寸的翻译后备缓冲区

    公开(公告)号：US5907867A

    公开(公告)日：1999-05-25

    申请号：US657231

    申请日：1996-06-03

    申请人： Toshinobu Shinbo ,  Suguru Tachibana ,  Susumu Narita ,  Shinichi Yoshioka ,  Koichiro Ishibashi ,  Hisayuki Higuchi ,  Yoshinobu Nakagome ,  Ikuya Kawasaki ,  Saneaki Tamaki

    发明人： Toshinobu Shinbo ,  Suguru Tachibana ,  Susumu Narita ,  Shinichi Yoshioka ,  Koichiro Ishibashi ,  Hisayuki Higuchi ,  Yoshinobu Nakagome ,  Ikuya Kawasaki ,  Saneaki Tamaki

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1027 ,  G06F2212/652 ,  Y02B60/1225

    摘要： A semiconductor integrated circuit device such as a data processing device having a set-associative translation look-aside buffer (TLB). A plurality of address arrays each have a second field for storing the value representing a page size. The values read from the second fields are used to change the range of address comparison by comparators. A plurality of data arrays each have a second field for storing a bit position address designating either an intra-page address or a page number following a page size change. The values read from the second fields of the address arrays are used as the basis for second selectors to select either an address in a predetermined location of an externally input virtual address or the address read from each of the second fields of the data arrays. The selected address is output as a physical address.

    摘要翻译： 一种半导体集成电路装置，例如具有集相关翻译后备缓冲器（TLB）的数据处理装置。 多个地址阵列各自具有用于存储表示页面大小的值的第二字段。 从第二个字段读取的值用于通过比较器更改地址比较范围。 多个数据阵列各自具有用于存储指定页面大小改变之后的页内地址或页码的位位置地址的第二字段。 从地址阵列的第二个字段读取的值被用作第二选择器选择外部输入的虚拟地址的预定位置的地址或从数据阵列的每个第二场读取的地址的基础。 所选地址作为物理地址输出。

    Accessing exception handlers without translating the address
    6.
    发明授权
    Accessing exception handlers without translating the address 失效
    访问异常处理程序而不转换地址

    公开(公告)号：US06425039B2

    公开(公告)日：2002-07-23

    申请号：US09450894

    申请日：1999-11-29

    申请人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Shigezumi Matsui ,  Susumu Narita

    发明人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Shigezumi Matsui ,  Susumu Narita

    IPC分类号： G06F1332

    CPC分类号： G06F9/32 ,  G06F9/30101

    摘要： A vector point of an exception handler related to TLB miss exception events is obtained by reading a vector base address of a register VBR one time, and by adding a vector offset (H′400) thereto. A vector point of an exception handler related to exception events other than the TLB miss exception events is obtained by adding a vector offset to a value (vector base address) of the register VBR, and an exception code which is an address offset obtained by reading a value of the register EXPEVT or INTEVT one time is added to the vector point that is obtained. Thus, the processing is branched to a required exception handler to execute the exception event processing related to exception events other than the TLB miss exception events.

    摘要翻译： 通过读取寄存器VBR的向量基地址一次并通过向其中添加向量偏移（H'400）来获得与TLB未命中异常事件相关的异常处理程序的向量点。 通过向寄存器VBR的值（向量基地址）添加矢量偏移，以及通过读取得到的地址偏移的异常代码，获得与除了TLB未命中异常事件之外的异常事件相关的异常处理程序的向量点 寄存器EXPEVT或INTEVT的值一次被添加到所获得的向量点。 因此，处理被分支到所需的异常处理程序，以执行与除了TLB未命中异常事件之外的异常事件相关的异常事件处理。

    Data processor having an address translation buffer operable with variable page sizes
    7.
    发明授权
    Data processor having an address translation buffer operable with variable page sizes 失效
    数据处理器具有可操作的可变页大小的地址转换缓冲器

    公开(公告)号：US5796978A

    公开(公告)日：1998-08-18

    申请号：US524561

    申请日：1995-09-07

    申请人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Susumu Narita ,  Saneaki Tamaki

    发明人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Susumu Narita ,  Saneaki Tamaki

    IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/12

    CPC分类号： G06F12/1036 ,  G06F12/1027 ,  G06F2212/652 ,  Y02B60/1225

    摘要： A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses shared, in which the virtual page size can be set for each page and which includes a TLB to be shared among the plural virtual pages set in various manners. This TLB is provided with a latch field for latching a pair of the virtual page number and the physical page number. The maximum size of the virtual page to be supported is set to the power of two of the minimum size, and the bank number of the TLB is set to no less than the power of two of the former.

    摘要翻译： 能够支持多个页面大小而不增加芯片占用面积或功耗的数据处理器。 用于支持虚拟存储器的该数据处理器由具有共享其索引地址的多个存储体的集合关联型高速缓存存储器构成，其中可以为每个页面设置虚拟页面大小，并且其中包括要在每个页面之间共享的TLB 多个虚拟页面以各种方式设置。 该TLB具有用于锁存一对虚拟页码和物理页号的锁存字段。 要支持的虚拟页面的最大大小设置为最小大小的两倍，并且TLB的存储区号设置为不小于前者中两个的大小。

    Processor with an addressable address translation buffer operative in associative and non-associative modes
    8.
    发明授权
    Processor with an addressable address translation buffer operative in associative and non-associative modes 失效
    具有可寻址地址转换缓冲器的处理器以联合和非关联模式运行

    公开(公告)号：US5835963A

    公开(公告)日：1998-11-10

    申请号：US524791

    申请日：1995-09-07

    申请人： Shinichi Yoshioka ,  Susumu Narita ,  Ikuya Kawasaki ,  Saneaki Tamaki

    发明人： Shinichi Yoshioka ,  Susumu Narita ,  Ikuya Kawasaki ,  Saneaki Tamaki

    IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G06F12/14 ,  G11C29/24

    CPC分类号： G06F12/1054 ,  G11C29/24 ,  G06F2212/2515

    摘要： A data processor supporting associative writing and comprising an associative memory and a central processing unit, the associative memory being furnished in the address space managed by the central processing unit. Any of the entries in the memory is accessed when the address of the entry in question in the address space is designated. With associative writing supported, data is allowed to be written to the designated address if the searched address information retained in the entry at the designated address matches the corresponding information held in the write data upon comparison. The write data is inhibited from being written to the designated address in case of a mismatch between the two kinds of information.

    摘要翻译： 一种支持关联写入并包括关联存储器和中央处理单元的数据处理器，所述关联存储器被提供在由所述中央处理单元管理的地址空间中。 当指定地址空间中有问题的条目的地址时，访问存储器中的任何条目。 如果支持相关写入，则如果在指定地址的条目中保留的搜索到的地址信息与比较时写入数据中保存的相应信息相匹配，则允许将数据写入指定地址。 在两种信息不匹配的情况下，写入数据被禁止写入指定的地址。

    Data processor for implementing virtual pages using a cache and register
    9.
    发明授权
    Data processor for implementing virtual pages using a cache and register 失效
    数据处理器，用于使用缓存和寄存器实现虚拟页面

    公开(公告)号：US6047354A

    公开(公告)日：2000-04-04

    申请号：US7249

    申请日：1998-01-14

    申请人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Susumu Narita ,  Saneaki Tamaki

    发明人： Shinichi Yoshioka ,  Ikuya Kawasaki ,  Susumu Narita ,  Saneaki Tamaki

    IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/12 ,  G11C15/00

    CPC分类号： G06F12/1036 ,  G06F12/1027 ,  G06F2212/652 ,  Y02B60/1225

    摘要： A data processor capable of supporting a plurality of page sizes without increasing the chip occupation area or the power consumption. This data processor for supporting a virtual memory is constructed of a set associative type cache memory having a plurality of banks having their index addresses shared, in which the virtual page size can be set for each page and which includes a TLB to be shared among the plural virtual pages set in various manners. This TLB is provided with a latch field for latching a pair of the virtual page number and the physical page number. The maximum size of the virtual page to be supported is set to the power of two of the minimum size, and the bank number of the TLB is set to no less than the power of two of the former.

    摘要翻译： 能够支持多个页面大小而不增加芯片占用面积或功耗的数据处理器。 用于支持虚拟存储器的该数据处理器由具有共享其索引地址的多个存储体的集合关联型高速缓存存储器构成，其中可以为每个页面设置虚拟页面大小，并且其中包括要在每个页面之间共享的TLB 多个虚拟页面以各种方式设置。 该TLB具有用于锁存一对虚拟页码和物理页号的锁存字段。 要支持的虚拟页面的最大大小设置为最小大小的两倍，并且TLB的存储区号设置为不小于前者中两个的大小。

    Microprocessor operating at high and low clok frequencies
    10.
    发明授权
    Microprocessor operating at high and low clok frequencies 失效
    微处理器工作在高低低频率

    公开(公告)号：US5774701A

    公开(公告)日：1998-06-30

    申请号：US500227

    申请日：1995-07-10

    申请人： Shigezumi Matsui ,  Mitsuyoshi Yamamoto ,  Shinichi Yoshioka ,  Susumu Narita ,  Ikuya Kawasaki ,  Susumu Kaneko ,  Kiyoshi Hasegawa

    发明人： Shigezumi Matsui ,  Mitsuyoshi Yamamoto ,  Shinichi Yoshioka ,  Susumu Narita ,  Ikuya Kawasaki ,  Susumu Kaneko ,  Kiyoshi Hasegawa

    IPC分类号： G06F1/08 ,  G06F1/04

    CPC分类号： G06F1/08

    摘要： A microprocessor incorporating a PLL circuit using a clock pulse having a relatively low frequency as an input clock signal of a reference frequency to form an oscillating pulse of a relatively high frequency by multiplying the input clock signal. In the microprocessor, the operation of the PLL circuit is stopped in the low-speed mode to supply the clock pulse of the relatively low frequency to the microprocessor as a system clock signal, and, in the high-speed mode, the PLL circuit is activated upon reception of an event requiring high-speed processing. Until the operation of the PLL circuit is stabilized and the request for high-speed processing comes, the above-mentioned clock pulse having the relatively low frequency is kept supplied continuously to the microprocessor as the system clock signal. This novel setup permits the high-speed switching of the microprocessor from the operating mode to the high-speed operating mode. Accordingly, the microprocessor may be kept operating until the output frequency of the PLL circuit is stabilized, thereby allowing the microprocessor to cope with an unpredictable situation such as the occurrence of a priority event or a failure.

    摘要翻译： 一种微处理器，其使用具有相对较低频率的时钟脉冲的PLL电路作为参考频率的输入时钟信号，以通过乘以输入时钟信号来形成相对高频率的振荡脉冲。 在微处理器中，PLL电路的操作在低速模式下停止，以较低频率的时钟脉冲作为系统时钟信号供给微处理器，在高速模式下，PLL电路为 在接收到需要高速处理的事件时被激活。 直到PLL电路的操作稳定并且高速处理的请求到来之前，具有较低频率的上述时钟脉冲作为系统时钟信号被连续地提供给微处理器。 这种新颖的设置允许微处理器从操作模式到高速操作模式的高速切换。 因此，微处理器可以保持工作，直到PLL电路的输出频率稳定，从而允许微处理器处理诸如发生优先事件或故障的不可预知的情况。