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    Cache memory employing dynamically controlled data array start timing and a microprocessor using the same
    1.
    发明授权
    Cache memory employing dynamically controlled data array start timing and a microprocessor using the same 失效
    使用动态控制的数据阵列启动定时的高速缓存存储器和使用其的微处理器

    公开(公告)号：US06389523B1

    公开(公告)日：2002-05-14

    申请号：US09557220

    申请日：2000-04-25

    申请人： Yasuhisa Shimazaki ,  Seiichi Nagata ,  Katuhiro Norisue ,  Koichiro Ishibashi ,  Junichi Nishimoto ,  Shinichi Yoshioka ,  Susumu Narita

    发明人： Yasuhisa Shimazaki ,  Seiichi Nagata ,  Katuhiro Norisue ,  Koichiro Ishibashi ,  Junichi Nishimoto ,  Shinichi Yoshioka ,  Susumu Narita

    IPC分类号： G06F1206

    CPC分类号： G06F12/0864 ,  G06F2212/1028 ,  Y02D10/13

    摘要： A comparator is constituted such that a hit signal &phgr;hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.

    摘要翻译： 构成一个比较器，使命中信号phihit是高的，在地址阵列的每个方式建立命中检查之前，并且当已经建立了一个错误时，命中信号变低。 当时钟频率相对较高时，地址阵列由第一时钟信号激活，此后，在地址阵列中的命中检查建立之前，数据阵列的所有方式都被第二时钟信号激活。 当命中检查已经建立时，从命中的数据阵列中读取的数据被立即输出到数据线上，并以停止的方式进行操作。 这种新颖的结构实现了高速缓存操作。 当时钟频率相对较低时，在命中检查完成之后仅激活已经命中的数据阵列中的一种方式，从而降低了低速操作时的功耗。

    Cache memory employing dynamically controlled data array start timing and a microcomputer using the same
    2.
    发明授权
    Cache memory employing dynamically controlled data array start timing and a microcomputer using the same 失效
    使用动态控制的数据阵列启动定时的高速缓冲存储器和使用其的微型计算机

    公开(公告)号：US5860127A

    公开(公告)日：1999-01-12

    申请号：US653278

    申请日：1996-05-24

    申请人： Yasuhisa Shimazaki ,  Seiichi Nagata ,  Katuhiro Norisue ,  Koichiro Ishibashi ,  Junichi Nishimoto ,  Shinichi Yoshioka ,  Susumu Narita

    发明人： Yasuhisa Shimazaki ,  Seiichi Nagata ,  Katuhiro Norisue ,  Koichiro Ishibashi ,  Junichi Nishimoto ,  Shinichi Yoshioka ,  Susumu Narita

    IPC分类号： G06F12/00 ,  G06F12/06 ,  G06F12/08

    CPC分类号： G06F12/0864 ,  G06F2212/1028 ,  Y02B60/1225

    摘要： A comparator is constituted such that a hit signal .phi.hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.

    摘要翻译： 构成比较器，使得命中信号phi命中为高，在地址阵列的每个方式建立命中检查之前，并且当已经建立了一个虚构时，命中信号变低。 当时钟频率相对较高时，地址阵列由第一时钟信号激活，此后，在地址阵列中的命中检查建立之前，数据阵列的所有方式都被第二时钟信号激活。 当命中检查已经建立时，从命中的数据阵列中读取的数据被立即输出到数据线上，并以停止的方式进行操作。 这种新颖的结构实现了高速缓存操作。 当时钟频率相对较低时，在命中检查完成之后仅激活已经命中的数据阵列中的一种方式，从而降低了低速操作时的功耗。

    Cacche memory employing dynamically controlled data array start timing and a microcomputer using the same
    3.
    发明授权
    Cacche memory employing dynamically controlled data array start timing and a microcomputer using the same 失效
    采用动态控制的数据阵列启动定时的Cacche存储器和使用它的微型计算机

    公开(公告)号：US6070234A

    公开(公告)日：2000-05-30

    申请号：US118892

    申请日：1998-07-20

    申请人： Yasuhisa Shimazaki ,  Seiichi Nagata ,  Katuhiro Norisue ,  Koichiro Ishibashi ,  Junichi Nishimoto ,  Shinichi Yoshioka ,  Susumu Narita

    发明人： Yasuhisa Shimazaki ,  Seiichi Nagata ,  Katuhiro Norisue ,  Koichiro Ishibashi ,  Junichi Nishimoto ,  Shinichi Yoshioka ,  Susumu Narita

    IPC分类号： G06F12/00 ,  G06F12/06 ,  G06F12/08

    CPC分类号： G06F12/0864 ,  G06F2212/1028 ,  Y02B60/1225

    摘要： A comparator is constituted such that a hit signal .phi.hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.

    摘要翻译： 构成比较器，使得命中信号phi命中为高，在地址阵列的每个方式建立命中检查之前，并且当已经建立了一个虚构时，命中信号变低。 当时钟频率相对较高时，地址阵列由第一时钟信号激活，此后，在地址阵列中的命中检查建立之前，数据阵列的所有方式都被第二时钟信号激活。 当命中检查已经建立时，从命中的数据阵列中读取的数据被立即输出到数据线上，并以停止的方式进行操作。 这种新颖的结构实现了高速缓存操作。 当时钟频率相对较低时，在命中检查完成之后仅激活已经命中的数据阵列中的一种方式，从而降低了低速操作时的功耗。

    Translation lookaside buffer supporting multiple page sizes
    5.
    发明授权
    Translation lookaside buffer supporting multiple page sizes 失效
    支持多页尺寸的翻译后备缓冲区

    公开(公告)号：US5907867A

    公开(公告)日：1999-05-25

    申请号：US657231

    申请日：1996-06-03

    申请人： Toshinobu Shinbo ,  Suguru Tachibana ,  Susumu Narita ,  Shinichi Yoshioka ,  Koichiro Ishibashi ,  Hisayuki Higuchi ,  Yoshinobu Nakagome ,  Ikuya Kawasaki ,  Saneaki Tamaki

    发明人： Toshinobu Shinbo ,  Suguru Tachibana ,  Susumu Narita ,  Shinichi Yoshioka ,  Koichiro Ishibashi ,  Hisayuki Higuchi ,  Yoshinobu Nakagome ,  Ikuya Kawasaki ,  Saneaki Tamaki

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1027 ,  G06F2212/652 ,  Y02B60/1225

    摘要： A semiconductor integrated circuit device such as a data processing device having a set-associative translation look-aside buffer (TLB). A plurality of address arrays each have a second field for storing the value representing a page size. The values read from the second fields are used to change the range of address comparison by comparators. A plurality of data arrays each have a second field for storing a bit position address designating either an intra-page address or a page number following a page size change. The values read from the second fields of the address arrays are used as the basis for second selectors to select either an address in a predetermined location of an externally input virtual address or the address read from each of the second fields of the data arrays. The selected address is output as a physical address.

    摘要翻译： 一种半导体集成电路装置，例如具有集相关翻译后备缓冲器（TLB）的数据处理装置。 多个地址阵列各自具有用于存储表示页面大小的值的第二字段。 从第二个字段读取的值用于通过比较器更改地址比较范围。 多个数据阵列各自具有用于存储指定页面大小改变之后的页内地址或页码的位位置地址的第二字段。 从地址阵列的第二个字段读取的值被用作第二选择器选择外部输入的虚拟地址的预定位置的地址或从数据阵列的每个第二场读取的地址的基础。 所选地址作为物理地址输出。

    Substrate bias switching unit for a low power processor
    10.
    发明授权
    Substrate bias switching unit for a low power processor 有权
    用于低功耗处理器的基板偏置开关单元

    公开(公告)号：US07475261B2

    公开(公告)日：2009-01-06

    申请号：US10768136

    申请日：2004-02-02

    申请人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

    发明人： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

    IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

    摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

    摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。