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    Semiconductor memory device having high-concentration region around electric-field moderating layer in substrate
    2.
    发明授权
    Semiconductor memory device having high-concentration region around electric-field moderating layer in substrate 失效
    半导体存储器件在衬底内具有围绕电场调节层的高浓度区域

    公开(公告)号：US06236085B1

    公开(公告)日：2001-05-22

    申请号：US08966707

    申请日：1997-11-10

    申请人： Tsutomu Kawaguchi ,  Mitsutaka Katada

    发明人： Tsutomu Kawaguchi ,  Mitsutaka Katada

    IPC分类号： H01L2976

    CPC分类号： H01L29/7885 ,  Y10S257/90

    摘要： A semiconductor memory device comprising a source and a drain formed in a P-type semiconductor substrate and a floating gate and a control gate constituting a two-layer gate. Electric-field moderating layer is provided in the P-type semiconductor substrate to contact with a side face of the drain. P-type region is formed in contact with channel region side surface and bottom surface of the electric-field moderating layer. P-type region lower part of the P-type region in contact with the bottom surface of the electric-field moderating layer is given a lower impurity concentration than P-type region side part formed at the channel region side of the electric-field moderating layer. By this means it is possible to increase the writing speed of the semiconductor memory device while suppressing delay in the switching speed during reading operation.

    摘要翻译： 一种半导体存储器件，包括在P型半导体衬底中形成的源极和漏极，以及构成双层栅极的浮动栅极和控制栅极。 电场调节层设置在P型半导体衬底中以与漏极的侧面接触。 P型区域形成为与电场调节层的沟道区域侧表面和底面接触。 与电场调节层的底面接触的P型区域的P型区域下部的杂质浓度比形成在电场调节剂的通道区域侧的P型区域侧部分 层。 通过这种方式，可以在读取操作期间抑制开关速度的延迟来提高半导体存储器件的写入速度。

    Charge retention lifetime evaluation method for nonvolatile semiconductor memory
    6.
    发明授权
    Charge retention lifetime evaluation method for nonvolatile semiconductor memory 有权
    非易失性半导体存储器的充电保持寿命评估方法

    公开(公告)号：US06339557B1

    公开(公告)日：2002-01-15

    申请号：US09583868

    申请日：2000-05-31

    申请人： Tsutomu Kawaguchi ,  Shigemitsu Fukatsu ,  Mitsutaka Katada

    发明人： Tsutomu Kawaguchi ,  Shigemitsu Fukatsu ,  Mitsutaka Katada

    IPC分类号： G11C704

    CPC分类号： G11C29/50004 ,  G11C16/04 ,  G11C29/50 ,  G11C29/50016

    摘要： In a nonvolatile semiconductor memory, a floating gate electrode is disposed above a silicon substrate between source and drain regions, through a tunnel film, and a control gate electrode is disposed above the floating gate electrode through an insulating film. The substrate is grounded and at least two negative voltages are respectively applied to the control gate electrode, so that a voltage is applied to the tunnel film. In these cases, charge retention properties are evaluated. The voltages applied to the control gate electrode are controlled so that the voltage applied to the tunnel film does not exceed a voltage applied to the tunnel film during a memory operation. A charge retention property when no voltage is applied across the control gate electrode and the substrate, i.e., when no voltage is externally applied to the tunnel film, is estimated by the charge retention properties when the two voltages are applied to the control gate electrode.

    摘要翻译： 在非易失性半导体存储器中，浮栅电极通过隧道膜设置在源极和漏极区域之间的硅衬底之上，并且控制栅电极通过绝缘膜设置在浮栅上。 衬底接地，并且至少两个负电压分别施加到控制栅电极，使得电压施加到隧道膜。 在这些情况下，评估电荷保留性能。 控制施加到控制栅电极的电压，使得施加到隧道膜的电压在存储操作期间不超过施加到隧道膜的电压。 当控制栅电极和基板两端施加电压时，即当没有施加电压到隧道膜时，电荷保持性能通过电荷保持特性来估计，当两个电压施加到控制栅电极时。

    Semiconductor device and fabrication process thereof
    9.
    发明授权
    Semiconductor device and fabrication process thereof 失效
    半导体器件及其制造工艺

    公开(公告)号：US06337249B1

    公开(公告)日：2002-01-08

    申请号：US09715052

    申请日：2000-11-20

    申请人： Hiroyuki Yamane ,  Yasushi Higuchi ,  Mitsutaka Katada ,  Noriyuki Iwamori ,  Tsutomu Kawaguchi ,  Takeshi Kuzuhara

    发明人： Hiroyuki Yamane ,  Yasushi Higuchi ,  Mitsutaka Katada ,  Noriyuki Iwamori ,  Tsutomu Kawaguchi ,  Takeshi Kuzuhara

    IPC分类号： H01L21336

    CPC分类号： H01L29/66659 ,  H01L27/088 ,  H01L27/112 ,  H01L29/1045 ,  H01L29/1083

    摘要： A semiconductor device having an enhancement-type MOS structure which can prevent large leakage current is disclosed. A high-concentration region for threshold-value regulation use formed in a channel region below a gate electrode in an enhancement-type transistor is caused to be contiguous with a source region and not contiguous with a drain region. Herein, the distance between the high-concentration region and the drain region is set so as to preclude the depletion layer extending from the drain region side from reaching the high-concentration region. Therefore, the electrical field in the depletion layer does not become the critical field which causes avalanche or Zener breakdown, and so leakage current can be caused to be reduced.

    摘要翻译： 公开了一种能够防止大的漏电流的具有增强型MOS结构的半导体器件。 导致在增强型晶体管中形成在栅电极下方的沟道区域中的阈值调节用途的高浓度区域与源极区域连续并且不与漏极区域邻接。 这里，设定高浓度区域和漏极区域之间的距离，以防止从漏极区域侧延伸的耗尽层到达高浓度区域。 因此，耗尽层中的电场不会成为引起雪崩或齐纳击穿的关键场，因此可以减少漏电流。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5986302A

    公开(公告)日：1999-11-16

    申请号：US18305

    申请日：1998-02-03

    申请人： Shigemitsu Fukatsu ,  Tsutomu Kawaguchi ,  Takuya Okuno ,  Yukiaki Yogo

    发明人： Shigemitsu Fukatsu ,  Tsutomu Kawaguchi ,  Takuya Okuno ,  Yukiaki Yogo

    IPC分类号： H01L21/28 ,  H01L29/788 ,  H01L29/76 ,  H01L29/792

    CPC分类号： H01L21/28273 ,  H01L29/7885

    摘要： A floating gate of a semiconductor memory device has a gate bird beak on an end portion thereof. Further, a positional relationship between the floating gate and a drain is controlled such that a depletion layer formed within the drain in a non-selected state of the semiconductor memory device faces the gate bird beak without interposing the drain therebetween. Accordingly, drain disturbance can be efficiently prevented.

    摘要翻译： 半导体存储器件的浮置栅极在其端部具有栅极鸟嘴。 此外，控制浮置栅极和漏极之间的位置关系，使得形成在半导体存储器件的未选择状态的漏极内的耗尽层面对栅极鸟嘴而不在其间插入漏极。 因此，能够有效地防止漏极干扰。