公开(公告)号：US5388084A

公开(公告)日：1995-02-07

申请号：US128087

申请日：1993-09-29

申请人： Yasuo Itoh ,  Sumio Tanaka ,  Junichi Miyamoto ,  Hiroshi Nakamura ,  Yoshihisa Iwata ,  Kenichi Imamiya ,  Yoshihisa Sugiura

发明人： Yasuo Itoh ,  Sumio Tanaka ,  Junichi Miyamoto ,  Hiroshi Nakamura ,  Yoshihisa Iwata ,  Kenichi Imamiya ,  Yoshihisa Sugiura

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

CPC分类号： G11C5/147 ,  G11C16/30

摘要： Disclosed is a semiconductor integrated circuit device, which comprises a booster circuit for boosting a source voltage, a voltage limiter having one end connected to the output terminal of the booster circuit, for limiting the output voltage of the booster circuit to a given value, and a voltage setting circuit, connected to the other end of the voltage limiter, for arbitrarily adjusting a voltage at the other end of the voltage limiter. This design can keep the output voltage of the booster circuit at a constant level and can set that output voltage to an arbitrary voltage.

摘要翻译： 公开了一种半导体集成电路装置，其包括用于升压源极电压的升压电路，具有连接到升压电路的输出端子的一端的限压器，用于将升压电路的输出电压限制在给定值，以及 连接到限压器的另一端的电压设定电路，用于任意地调节限压器另一端的电压。 该设计可以将升压电路的输出电压保持在恒定电平，并可将该输出电压设置为任意电压。

公开(公告)号：US06590444B2

公开(公告)日：2003-07-08

申请号：US10200152

申请日：2002-07-23

申请人： Tamio Ikehashi ,  Yoshihisa Sugiura ,  Kenichi Imamiya ,  Ken Takeuchi ,  Yoshihisa Iwata

发明人： Tamio Ikehashi ,  Yoshihisa Sugiura ,  Kenichi Imamiya ,  Ken Takeuchi ,  Yoshihisa Iwata

IPC分类号： G05F302

CPC分类号： G05F1/465

摘要： In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode. A down converter is formed in a lower layer of an external power supply line and peripheral circuit blocks are arranged in a lower layer of internal power supply lines on both sides of the external power supply line symmetrically with respect thereto, whereby a power supply distance of the power supply voltage is minimized and controllability of the internal power supply voltage is improved.

摘要翻译： 为了避免暂时改变电源电压的任何故障，并且当从待机模式转换到主动模式时抑制内部电源电压的降低，所公开的半导体集成电路设置有防止 通过根据电源电压何时增加或减少来改变检测电平而发生电源电压暂时改变的故障。 此外，通过在待机模式中采用PMOS下变频器和在活动模式中的NMOS下变频器来抑制从待机模式转换到有功模式之后的内部电源电压的降低，并且设置 处于待机模式的PMOS下变频器的内部电源电压高于活动模式。 下变频器形成在外部电源线的下层中，并且外围电路块相对于其对称地布置在外部电源线的两侧的内部电源线的下层中，从而电源距离 电源电压最小化，内部电源电压的可控性提高。

公开(公告)号：US06351179B1

公开(公告)日：2002-02-26

申请号：US09375370

申请日：1999-08-17

申请人： Tamio Ikehashi ,  Yoshihisa Sugiura ,  Kenichi Imamiya ,  Ken Takeuchi ,  Yoshihisa Iwata

发明人： Tamio Ikehashi ,  Yoshihisa Sugiura ,  Kenichi Imamiya ,  Ken Takeuchi ,  Yoshihisa Iwata

IPC分类号： G05F110

CPC分类号： G05F1/465

摘要： In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode. A down converter is formed in a lower layer of an external power supply line and peripheral circuit blocks are arranged in a lower layer of internal power supply lines on both sides of the external power supply line symmetrically with respect thereto, whereby a power supply distance of the power supply voltage is minimized and controllability of the internal power supply voltage is improved.

摘要翻译： 为了避免暂时改变电源电压的任何故障，并且当从待机模式转换到主动模式时抑制内部电源电压的降低，所公开的半导体集成电路设置有防止 通过根据电源电压何时增加或减少来改变检测电平而发生电源电压暂时改变的故障。 此外，通过在待机模式中采用PMOS下变频器和在激活模式下的NMOS下变频器来抑制从待机模式转换到有功模式之后的内部电源电压的降低，并且设置 处于待机模式的PMOS下变频器的内部电源电压高于活动模式。 下变频器形成在外部电源线的下层中，并且外围电路块相对于其对称地布置在外部电源线的两侧的内部电源线的下层中，从而电源距离 电源电压最小化，内部电源电压的可控性提高。

公开(公告)号：US06801060B2

公开(公告)日：2004-10-05

申请号：US10443820

申请日：2003-05-23

申请人： Tamio Ikehashi ,  Yoshihisa Sugiura ,  Kenichi Imamiya ,  Ken Takeuchi ,  Yoshihisa Iwata

发明人： Tamio Ikehashi ,  Yoshihisa Sugiura ,  Kenichi Imamiya ,  Ken Takeuchi ,  Yoshihisa Iwata

IPC分类号： H03K5153

CPC分类号： G05F1/465

摘要： In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode. A down converter is formed in a lower layer of an external power supply line and peripheral circuit blocks are arranged in a lower layer of internal power supply lines on both sides of the external power supply line symmetrically with respect thereto, whereby a power supply distance of the power supply voltage is minimized and controllability of the internal power supply voltage is improved.

摘要翻译： 为了避免暂时改变电源电压的任何故障，并且当从待机模式转换到主动模式时抑制内部电源电压的降低，所公开的半导体集成电路设置有防止 通过根据电源电压何时增加或减少来改变检测电平而发生电源电压暂时改变的故障。 此外，通过在待机模式中采用PMOS下变频器和在活动模式中的NMOS下变频器来抑制从待机模式转换到有功模式之后的内部电源电压的降低，并且设置 处于待机模式的PMOS下变频器的内部电源电压高于活动模式。 下变频器形成在外部电源线的下层中，并且外围电路块相对于其对称地布置在外部电源线的两侧的内部电源线的下层中，从而电源距离 电源电压最小化，内部电源电压的可控性提高。

公开(公告)号：US5327395A

公开(公告)日：1994-07-05

申请号：US957000

申请日：1992-10-06

申请人： Yoshihisa Sugiura ,  Yoshihisa Iwata ,  Masaki Momodomi ,  Yasuo Itoh ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

发明人： Yoshihisa Sugiura ,  Yoshihisa Iwata ,  Masaki Momodomi ,  Yasuo Itoh ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/08 ,  G11C16/10 ,  G11C8/00

CPC分类号： G11C16/08 ,  G11C16/10 ,  G11C2216/14

摘要： A NOR operation is performed on the address bit by bit by a NOR circuit, and when the final address in a page is detected from the result of the NOR operation by a final address detection circuit, a program starting circuit executes data writing to a memory cell. This can ensure detection of the final address in a page without using a counter circuit. It is therefore possible to simplify the structure of the final address detection circuit and reduce the circuit area occupying in a semiconductor memory device.

摘要翻译： 通过NOR电路对地址逐位执行NOR运算，并且当由最终地址检测电路从NOR运算的结果检测到页面中的最终地址时，程序启动电路执行向存储器的数据写入 细胞。 这可以确保在不使用计数器电路的情况下检测页面中的最终地址。 因此，可以简化最终地址检测电路的结构并减少半导体存储器件占用的电路面积。

公开(公告)号：US6023424A

公开(公告)日：2000-02-08

申请号：US213411

申请日：1998-12-17

申请人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

发明人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

IPC分类号： G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/3454 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1048

摘要： A non-volatile semiconductor memory device comprises a flip-flop circuit for holding write data in one of first and second states, a bit line connected to the flip-flop circuit via a switching element, a transistor for charging the bit line, a non-volatile memory cell, connected to the bit line and having a MOS transistor structure, for storing data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode said threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range, and a data setting circuit for connecting one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.

公开(公告)号：US5880994A

公开(公告)日：1999-03-09

申请号：US909727

申请日：1997-08-12

申请人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

发明人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

IPC分类号： G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/3454 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1048

摘要： A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element and a transistor charges the bit line and line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.

摘要翻译： 非挥发性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路。 位线通过开关元件连接到触发器电路，晶体管对位线和线进行充电。 连接到位线并具有MOS晶体管结构的非易失性存储单元将其阈值设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，存储单元的阈值 在触发器电路保持在第一状态的同时触发器电路保持在第二状态，并且当触发器电路保持在第二状态时阈值的偏移不被影响时，从第一阈值范围向第二阈值范围移位， 在写模式之后，当阈值保持在第二阈值范围内时，位线被充电晶体管保持在电荷电位。 数据设定电路在检测模式中位线处于充电电位时，将触发器电路的第一和第二信号节点之一连接到预定电位，从而将触发器电路设置为第二状态，而与 在验证模式之前的状态。

公开(公告)号：US06493267B2

公开(公告)日：2002-12-10

申请号：US09836264

申请日：2001-04-18

申请人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

发明人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

IPC分类号： G11C1604

CPC分类号： G11C16/3459 ,  G11C7/1006 ,  G11C7/1048 ,  G11C16/10 ,  G11C16/3454

摘要： A non-volatile semiconductor memory device comprises a flip-flop circuit for holding write data in one of first and second states, a bit line connected to the flip-flop circuit via a switching element, a transistor for charging the bit line, a non-volatile memory cell, connected to the bit line and having a MOS transistor structure, for storing data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode said threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range, and a data setting circuit for connecting one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.

摘要翻译： 一种非易失性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路，经由开关元件连接到触发器电路的位线，用于对位线充电的晶体管， 连接到位线并具有MOS晶体管结构的非易失性存储单元，用于当其阈值被设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，所述存储器单元的阈值为 当触发器电路保持在第一状态并且在触发器电路保持在第二状态时阈值的偏移不被影响，并且在验证时，从第一阈值范围向第二阈值范围移动 模式下，当阈值保持在第二阈值范围内时，位线由充电晶体管保持在充电电位，并且数据设置电路用于连接第一和第二信号节点之一 当位线在验证模式下处于电荷电位时，触发电路的电位达到预定电位，从而将触发器电路设置在第二状态，而与验证模式之前的状态无关。

公开(公告)号：US06240018B1

公开(公告)日：2001-05-29

申请号：US09451142

申请日：1999-11-30

申请人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

发明人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

IPC分类号： G11C1606

CPC分类号： G11C16/3459 ,  G11C7/1006 ,  G11C7/1048 ,  G11C16/10 ,  G11C16/3454

摘要： A non-volatile semiconductor memory device comprises a flip-flop circuit for holding write data in one of first and second states, a bit line connected to the flip-flop circuit via a switching element, a transistor for charging the bit line, a non-volatile memory cell, connected to the bit line and having a MOS transistor structure, for storing data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode said threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range, and a data setting circuit for connecting one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.

摘要翻译： 一种非易失性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路，经由开关元件连接到触发器电路的位线，用于对位线充电的晶体管， 连接到位线并具有MOS晶体管结构的非易失性存储单元，用于当其阈值被设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，所述存储器单元的阈值为 当触发器电路保持在第一状态并且在触发器电路保持在第二状态时阈值的偏移不被影响，并且在验证时，从第一阈值范围向第二阈值范围移动 模式下，当阈值保持在第二阈值范围内时，位线由充电晶体管保持在充电电位，并且数据设置电路用于连接第一和第二信号节点之一 当位线在验证模式下处于电荷电位时，触发电路的电位达到预定电位，从而将触发器电路设置在第二状态，而与验证模式之前的状态无关。

公开(公告)号：US5726882A

公开(公告)日：1998-03-10

申请号：US659229

申请日：1996-06-05

申请人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

发明人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

IPC分类号： G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/3454 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1048

摘要： A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element and a transistor charges the bit line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.

摘要翻译： 非挥发性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路。 位线通过开关元件连接到触发器电路，并且晶体管对位线进行充电。 连接到位线并具有MOS晶体管结构的非易失性存储单元将其阈值设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，存储单元的阈值 在触发器电路保持在第一状态的同时触发器电路保持在第二状态，并且当触发器电路保持在第二状态时阈值的偏移不被影响时，从第一阈值范围向第二阈值范围移位， 在写模式之后，当阈值保持在第二阈值范围内时，位线被充电晶体管保持在电荷电位。 数据设定电路在检测模式中位线处于充电电位时，将触发器电路的第一和第二信号节点之一连接到预定电位，从而将触发器电路设置为第二状态，而与 在验证模式之前的状态。