公开(公告)号：US07276769B2

公开(公告)日：2007-10-02

申请号：US10817861

申请日：2004-04-06

申请人： Masaru Yamada ,  Yasutoshi Okuno

发明人： Masaru Yamada ,  Yasutoshi Okuno

IPC分类号： H01L29/72

CPC分类号： H01L27/0207

摘要： In a semiconductor integrated circuit device, semiconductor elements formed in active regions included in a first element formation portion (stress transition region) in a peripheral circuit formation portion are not electrically driven, while only semiconductor elements of a second element formation portion (steady stress region) are electrically driven. Therefore, the second element formation portion in the peripheral circuit formation portion is located away from an outer STI region so as to be hardly affected by compressive stress.

摘要翻译： 在半导体集成电路器件中，形成在周边电路形成部分的第一元件形成部分（应力过渡区域）中的有源区域中形成的半导体元件不被电驱动，而只有第二元件形成部分的半导体元件（稳定应力区域 ）是电驱动的。 因此，周边电路形成部中的第二元件形成部位远离外侧STI区域，难以受到压缩应力的影响。

公开(公告)号：US20050285217A1

公开(公告)日：2005-12-29

申请号：US11006665

申请日：2004-12-08

申请人： Yasutoshi Okuno ,  Masaru Yamada

发明人： Yasutoshi Okuno ,  Masaru Yamada

IPC分类号： H01L21/3105 ,  H01L21/76 ,  H01L21/762 ,  H01L27/02 ,  H01L29/00

CPC分类号： H01L21/31053 ,  H01L21/76229 ,  H01L27/0207

摘要： A semiconductor device includes a circuit formation region which is formed in a semiconductor substrate and includes a plurality of element formation regions surrounded by isolation regions, respectively. A stress effect relief region of a predetermined width is formed around the circuit formation region to relieve a stress effect of the isolation regions on the operation characteristics of elements formed in the element formation regions and a plurality of dummy features are formed in the stress effect relief region and other part of the circuit formation region than the element formation regions at predetermined distances, the dummy features having the same composition as the element formation regions and predetermined planar dimensions. The predetermined planar dimensions of the dummy features are defined by longitudinal and transverse dimensions most frequently found in the plurality of element formation regions formed in the circuit formation region or selected dimensions of the element formation regions. The predetermined distances between the dummy features are specified as the minimum allowable value in respect of the manufacture of the elements.

摘要翻译： 半导体器件包括电路形成区域，其形成在半导体衬底中并且包括被隔离区包围的多个元件形成区域。 在电路形成区域的周围形成预定宽度的应力作用缓和区域，以减轻隔离区域对形成在元件形成区域中的元件的操作特性的应力作用，并且在应力效应释放中形成多个虚拟特征 区域和电路形成区域的其他部分比元件形成区域预定距离，虚拟特征具有与元件形成区域相同的组成和预定的平面尺寸。 虚拟特征的预定平面尺寸由在电路形成区域中形成的多个元件形成区域或元件形成区域的选定尺寸中最常见的纵向和横向尺寸限定。 虚拟特征之间的预定距离被指定为关于元件的制造的最小允许值。

公开(公告)号：US07446015B2

公开(公告)日：2008-11-04

申请号：US11006665

申请日：2004-12-08

申请人： Yasutoshi Okuno ,  Masaru Yamada

发明人： Yasutoshi Okuno ,  Masaru Yamada

IPC分类号： H01L21/76

CPC分类号： H01L21/31053 ,  H01L21/76229 ,  H01L27/0207

摘要： A semiconductor device includes a circuit formation region which is formed in a semiconductor substrate and includes a plurality of element formation regions surrounded by isolation regions, respectively. A stress effect relief region of a predetermined width is formed around the circuit formation region to relieve a stress effect of the isolation regions on the operation characteristics of elements formed in the element formation regions and a plurality of dummy features are formed in the stress effect relief region and other part of the circuit formation region than the element formation regions at predetermined distances, the dummy features having the same composition as the element formation regions and predetermined planar dimensions. The predetermined planar dimensions of the dummy features are defined by longitudinal and transverse dimensions most frequently found in the plurality of element formation regions formed in the circuit formation region or selected dimensions of the element formation regions. The predetermined distances between the dummy features are specified as the minimum allowable value in respect of the manufacture of the elements.

摘要翻译： 半导体器件包括电路形成区域，其形成在半导体衬底中并且包括被隔离区包围的多个元件形成区域。 在电路形成区域的周围形成预定宽度的应力作用缓和区域，以减轻隔离区域对形成在元件形成区域中的元件的操作特性的应力作用，并且在应力效应释放中形成多个虚拟特征 区域和电路形成区域的其他部分比元件形成区域预定距离，虚拟特征具有与元件形成区域相同的组成和预定的平面尺寸。 虚拟特征的预定平面尺寸由在电路形成区域中形成的多个元件形成区域或元件形成区域的选定尺寸中最常见的纵向和横向尺寸限定。 虚拟特征之间的预定距离被指定为关于元件的制造的最小允许值。

公开(公告)号：US08084826B2

公开(公告)日：2011-12-27

申请号：US12364797

申请日：2009-02-03

申请人： Kenshi Kanegae ,  Masaru Yamada

发明人： Kenshi Kanegae ,  Masaru Yamada

IPC分类号： H01L21/66 ,  H01L21/76

CPC分类号： H01L21/823807 ,  H01L21/823412 ,  H01L21/823425 ,  H01L29/7843

摘要： An element larger than silicon is ion-implanted to a contact liner in an N-channel region to break constituent atoms of the contact liner in the N-channel region. An element larger than silicon is ion-implanted to the contact liner in a P-channel region to break constituent atoms of the contact liner, oxygen or the like is ion-implanted. Thereafter, heat treatment is performed to cause shrinkage of the contact liner in the N-channel region to form an n-channel contact liner, and to cause expansion of the contact liner in the P-channel region to form a p-channel contact liner.

摘要翻译： 将大于硅的元素离子注入N沟道区域中的接触衬垫，以破坏N沟道区中的接触衬垫的构成原子。 大于硅的元素被离子注入到P沟道区域中的接触衬垫上以破坏接触衬垫的构成原子，离子注入氧等。 然后，进行热处理，使N沟道区域的接触衬垫收缩，形成n沟道接触衬垫，使P沟道区域内的接触衬垫膨胀，形成p沟道接触衬垫 。

公开(公告)号：US07696099B2

公开(公告)日：2010-04-13

申请号：US11600068

申请日：2006-11-16

申请人： Masaru Yamada ,  Akihiko Tsudumitani

发明人： Masaru Yamada ,  Akihiko Tsudumitani

IPC分类号： H01L21/302

CPC分类号： H01L21/76232

摘要： A first film and a second film are formed on a semiconductor substrate in this order. A resist pattern is formed on the second film. An opening is formed by removing the second film exposed between the resist pattern at a state where the second film remains on the bottom. A first removal preventing film is formed on the side wall of the opening and the residual film is removed at a state where the projecting part of the second film protruding from the sidewall to the opening remains. The first film exposed in the opening is removed. A second removal preventing film is formed on the first removal preventing film and the surface of the semiconductor substrate exposed in the opening is removed at a state where the projecting part of the semiconductor substrate protruding from the side wall to the opening remains and a round part is formed at the projecting part of the semiconductor substrate. The semiconductor substrate exposed in the opening is further removed.

摘要翻译： 依次在半导体衬底上形成第一膜和第二膜。 在第二膜上形成抗蚀剂图案。 通过在第二膜保持在底部的状态下去除在抗蚀剂图案之间暴露的第二膜而形成开口。 在开口的侧壁上形成有第一去除防护膜，并且在从侧壁突出到开口部的第二膜的突出部分残留的状态下去除残留膜。 去除暴露在开口中的第一个薄膜。 在第一去除防止膜上形成第二防除去除膜，并且在从侧壁突出到开口的半导体衬底的突出部分残留的状态下去除在开口中暴露的半导体衬底的表面， 形成在半导体衬底的突出部分。 在开口中暴露的半导体衬底被进一步去除。

公开(公告)号：US20110001193A1

公开(公告)日：2011-01-06

申请号：US12882643

申请日：2010-09-15

申请人： Masaru Yamada ,  Masafumi Tsutsui ,  Kiyoyuki Morita

发明人： Masaru Yamada ,  Masafumi Tsutsui ,  Kiyoyuki Morita

IPC分类号： H01L27/092

CPC分类号： H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/7842 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor comprises an n-channel transistor forming region and a p-channel transistor forming region, which are disposed while being sectioned by an element isolation region. The stress caused by contact plugs in the n-channel transistor forming region and the stress caused by contact plugs in the p-channel transistor forming region are made different from each other. With this, it enables to increase the drive current of both the n-channel transistor and p-channel transistor without changing the dimensions of the active region and the element isolation region.

摘要翻译： 半导体包括n沟道晶体管形成区域和p沟道晶体管形成区域，它们被元件隔离区域划分。 在n沟道晶体管形成区域中由接触插塞引起的应力和由p沟道晶体管形成区域中的接触插塞引起的应力彼此不同。 由此，能够增加n沟道晶体管和p沟道晶体管的驱动电流，而不改变有源区和元件隔离区的尺寸。

公开(公告)号：US20090200582A1

公开(公告)日：2009-08-13

申请号：US12405668

申请日：2009-03-17

申请人： Masaru Yamada ,  Masafumi Tsutsui ,  Kiyoyuki Morita

发明人： Masaru Yamada ,  Masafumi Tsutsui ,  Kiyoyuki Morita

IPC分类号： H01L29/40

CPC分类号： H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823807 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/7842 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor comprises an n-channel transistor forming region and a p-channel transistor forming region, which are disposed while being sectioned by an element isolation region. The stress caused by contact plugs in the n-channel transistor forming region and the stress caused by contact plugs in the p-channel transistor forming region are made different from each other. With this, it enables to increase the drive current of both the n-channel transistor and p-channel transistor without changing the dimensions of the active region and the element isolation region.

摘要翻译： 半导体包括n沟道晶体管形成区域和p沟道晶体管形成区域，它们被元件隔离区域划分。 在n沟道晶体管形成区域中由接触插塞引起的应力和由p沟道晶体管形成区域中的接触插塞引起的应力彼此不同。 由此，能够增加n沟道晶体管和p沟道晶体管的驱动电流，而不改变有源区和元件隔离区的尺寸。

公开(公告)号：US20070196965A1

公开(公告)日：2007-08-23

申请号：US11600068

申请日：2006-11-16

申请人： Masaru Yamada ,  Akihiko Tsudumitani

发明人： Masaru Yamada ,  Akihiko Tsudumitani

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L21/76232

摘要： A first film and a second film are formed on a semiconductor substrate in this order. A resist pattern is formed on the second film. An opening is formed by removing the second film exposed between the resist pattern at a state where the second film remains on the bottom. A first removal preventing film is formed on the side wall of the opening and the residual film is removed at a state where the projecting part of the second film protruding from the sidewall to the opening remains. The first film exposed in the opening is removed. A second removal preventing film is formed on the first removal preventing film and the surface of the semiconductor substrate exposed in the opening is removed at a state where the projecting part of the semiconductor substrate protruding from the side wall to the opening remains and a round part is formed at the projecting part of the semiconductor substrate. The semiconductor substrate exposed in the opening is further removed.

摘要翻译： 依次在半导体衬底上形成第一膜和第二膜。 在第二膜上形成抗蚀剂图案。 通过在第二膜保持在底部的状态下去除在抗蚀剂图案之间暴露的第二膜而形成开口。 在开口的侧壁上形成有第一去除防护膜，并且在从侧壁突出到开口部的第二膜的突出部分残留的状态下去除残留膜。 去除暴露在开口中的第一个薄膜。 在第一去除防止膜上形成第二防除去除膜，并且在从侧壁突出到开口的半导体衬底的突出部分残留的状态下去除在开口中暴露的半导体衬底的表面， 形成在半导体衬底的突出部分。 在开口中暴露的半导体衬底被进一步去除。

公开(公告)号：US4410368A

公开(公告)日：1983-10-18

申请号：US309099

申请日：1981-10-06

申请人： Yoshiyuki Takasaki ,  Yoshimasa Takahara ,  Chikashi Izumi ,  Atsuhi Mori ,  Masahiko Nishiguchi ,  Masaru Yamada

发明人： Yoshiyuki Takasaki ,  Yoshimasa Takahara ,  Chikashi Izumi ,  Atsuhi Mori ,  Masahiko Nishiguchi ,  Masaru Yamada

IPC分类号： C12P19/14 ,  C12R1/07 ,  C13K1/06 ,  C13K7/00

CPC分类号： C13K1/06 ,  C12P19/14 ,  C13K7/00

摘要： A liquid starch solution suitable for saccharification into a maltose-containing product is obtained by suspending starch in water, adding to the starch suspension a heat resistant .alpha.-amylase and a buffer, adjusting the resultant mixture to a pH value in the range of from 7.5 to 8.0, and thermally treating the resultant starch milk while repressing possible hydrolysis of starch molecules.

摘要翻译： 通过将淀粉悬浮在水中得到适用于糖化成含麦芽糖的产品的液体淀粉溶液，向淀粉悬浮液中加入耐热的α-淀粉酶和缓冲液，将所得混合物调节至7.5的pH值 至8.0，并对所得淀粉乳进行热处理，同时抑制淀粉分子的可能水解。

公开(公告)号：US08293157B2

公开(公告)日：2012-10-23

申请号：US11989392

申请日：2006-05-10

申请人： Masaru Yamada ,  Kunihiro Ohshima

发明人： Masaru Yamada ,  Kunihiro Ohshima

IPC分类号： D01F2/08

CPC分类号： D01F2/08 ,  D01F4/00

摘要： A method of manufacturing a cellulose/gelatin composite viscose rayon filament that is characterized by including a process in which a spinning process is carried out while a viscose spinning solution is mixed with a gelatin crosslinking solution, which makes it possible to produce a cellulose/gelatin composite viscose rayon having uniform strength and elongation without yarn disconnection.

摘要翻译： 纤维素/明胶复合粘胶人造纤维丝的制造方法，其特征在于包括在粘胶纺丝溶液与明胶交联溶液混合的同时进行纺丝工序的方法，这使得可以生产纤维素/明胶 复合粘胶人造丝具有均匀的强度和伸长率，不脱纱。