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公开(公告)号：US20080077378A1
公开(公告)日：2008-03-27
申请号：US11822781
申请日：2007-07-10
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/5022
摘要： A circuit simulation apparatus has a means to acquire data regarding a transistor, a model parameter generation unit for generating a model parameter representing effects of stress upon the transistor active region caused by the isolation region, and a simulation execution unit for evaluating characteristics of the transistor using a simulation program associated with the model parameter. The model parameter includes a term regarding width of the transistor active region, a term regarding width of the peripheral active region, and a term regarding width between the transistor active region and the peripheral active region.
摘要翻译： 电路模拟装置具有获取关于晶体管的数据的模块，用于产生表示由隔离区域引起的晶体管有源区上的应力的影响的模型参数的模型参数生成单元，以及用于评估晶体管的特性的模拟执行单元 使用与模型参数相关联的模拟程序。 模型参数包括关于晶体管有源区的宽度的术语，关于外围有源区的宽度的术语，以及关于晶体管有源区和外围有源区之间的宽度的项。
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2.发明申请Method for designing semiconductor integrated circuit and method of circuit simulation 审中-公开半导体集成电路设计方法及电路仿真方法公开(公告)号：US20080021689A1
公开(公告)日：2008-01-24
申请号：US11812705
申请日：2007-06-21
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , G06F17/5036
摘要： By using, as a model expression, an expression showing an inverse proportion between a change rate ΔIdsat/Idsat of saturated current value and a product of a gate protrusion length E1 and a gate width Wg of a transistor and a coefficient, modeling is executed for a transistor property that depends on the gate protrusion length. This provides a circuit simulation that takes into consideration the gate protrusion length of a gate electrode.
摘要翻译： 通过使用作为模型表达式，表示在饱和电流值的变化率DeltaIdsat / Idsat与栅极突起长度E 1与晶体管的栅极宽度Wg的乘积与系数之间成反比的表达式，进行建模 对于取决于栅极突起长度的晶体管性质。 这提供了考虑栅电极的栅极突起长度的电路模拟。
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公开(公告)号：US20070018209A1
公开(公告)日：2007-01-25
申请号：US11410063
申请日：2006-04-25
申请人： Yasuyuki Sahara , Katsuhiro Ootani
发明人： Yasuyuki Sahara , Katsuhiro Ootani
CPC分类号： H01L27/092 , G06F17/5036 , H01L27/0207
摘要： A first PMIS transistor includes a first active region which is formed on a semiconductor substrate and a first gate electrode which is formed on the first active region and which is connected at one end thereof to a first gate wiring and includes at the other end thereof a first protruding portion protruding at a side opposite to the first gate wiring side from the first active region A first NMIS transistor includes a second active region which is formed on the semiconductor substrate with a space left from the first active region and a second gate electrode which is formed on the second active region and which is connected at one end thereof to the first gate wiring and includes at the other end thereof a second protruding portion protruding at a side opposite to the first gate wiring side from the second active region. A protruding length of the first protruding portion of the first PMIS transistor is greater than a protruding length of the second protruding portion of the first NMIS transistor.
摘要翻译： 第一PMIS晶体管包括形成在半导体衬底上的第一有源区和形成在第一有源区上的第一栅电极，该第一有源区的一端连接到第一栅极布线，另一端包括 第一突出部分在与第一有源区域A的第一栅极布线侧相对的一侧突出。第一NMIS晶体管包括形成在半导体衬底上的具有从第一有源区域剩下的空间的第二有源区和第二栅电极， 形成在所述第二有源区上，并且在其一端连接到所述第一栅极布线，并且在其另一端包括在与所述第二有源区的所述第一栅极布线侧相对的一侧突出的第二突出部。 第一PMIS晶体管的第一突出部分的突出长度大于第一NMIS晶体管的第二突出部分的突出长度。
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公开(公告)号：US07093215B2
公开(公告)日：2006-08-15
申请号：US10751892
申请日：2004-01-07
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , H01L27/0207
摘要： An inventive semiconductor circuit device includes an N-well and a P-well. The N-well is provided with PMIS active areas surrounded by a trench isolation, and the P-well is provided with NMIS active areas surrounded by the trench isolation. The PMIS active areas are each provided with a gate of a P-channel transistor, and the NMIS active areas are each provided with a gate of an N-channel transistor. A layout is designed such that a distance Dpn between the NMIS active areas and the PMIS active areas in a Y-direction substantially becomes a fixed value. Thus, trench isolation stresses applied from the trench isolations to channel regions under the gates become uniform for respective transistors, resulting in an improvement in accuracy of circuit simulation.
摘要翻译： 本发明的半导体电路器件包括N阱和P阱。 N阱具有被沟槽隔离环绕的PMIS有源区，并且P阱具有由沟槽隔离包围的NMIS有源区。 PMIS有源区域各自设置有P沟道晶体管的栅极，并且NMIS有源区域各自设置有N沟道晶体管的栅极。 设计布局，使得NMIS有效区域与Y方向上的PMIS有效区域之间的距离Dpn基本上变为固定值。 因此，从沟槽隔离施加到栅极下方的沟道区的沟槽隔离应力对于各个晶体管而变得均匀，导致电路仿真精度的提高。
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公开(公告)号：US20060142987A1
公开(公告)日：2006-06-29
申请号：US11313994
申请日：2005-12-22
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A circuit simulation apparatus and a modeling method are provided which are useful to design an integrated circuit in a very fine manner by forming a model of such a transistor that widths of element isolating-purpose insulating films are different from each other. In an isolation width depending parameter correcting means 4 of the present invention, an approximate expression of a parameter having an element isolating-purpose insulating film width depending characteristic is formed, and a value of a corrected parameter obtained by employing the formed approximate expression is replaced by a value of an original parameter, so that a transistor model of such a transistor is formed in which element isolating-purpose insulating film widths are different from each other. As a consequence, circuit simulation can be carried out in high precision by considering a change in transistor characteristics caused by a stress, which are approximated to actually measured data.
摘要翻译： 提供了一种电路模拟装置和建模方法，其通过形成元件隔离用绝缘膜的宽度彼此不同的这种晶体管的模型，以非常精细的方式设计集成电路是有用的。 在本发明的隔离宽度相关参数校正装置4中，形成具有元件隔离用绝缘膜宽度依赖特性的参数的近似表达式，并且替换通过使用形成的近似表达式而获得的校正参数的值 通过原始参数的值，使得形成这种晶体管的晶体管模型，其中元件隔离用绝缘膜宽度彼此不同。 因此，可以通过考虑由近似于实际测量数据的应力引起的晶体管特性的变化，可以高精度地进行电路仿真。
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公开(公告)号：US07462914B2
公开(公告)日：2008-12-09
申请号：US11410063
申请日：2006-04-25
申请人： Yasuyuki Sahara , Katsuhiro Ootani
发明人： Yasuyuki Sahara , Katsuhiro Ootani
IPC分类号： H01L29/78 , H01L21/8238 , G06F17/50
CPC分类号： H01L27/092 , G06F17/5036 , H01L27/0207
摘要： A first PMIS transistor includes a first active region which is formed on a semiconductor substrate and a first gate electrode which is formed on the first active region and which is connected at one end thereof to a first gate wiring and includes at the other end thereof a first protruding portion protruding at a side opposite to the first gate wiring side from the first active region A first NMIS transistor includes a second active region which is formed on the semiconductor substrate with a space left from the first active region and a second gate electrode which is formed on the second active region and which is connected at one end thereof to the first gate wiring and includes at the other end thereof a second protruding portion protruding at a side opposite to the first gate wiring side from the second active region. A protruding length of the first protruding portion of the first PMIS transistor is greater than a protruding length of the second protruding portion of the first NMIS transistor.
摘要翻译： 第一PMIS晶体管包括形成在半导体衬底上的第一有源区和形成在第一有源区上的第一栅电极，该第一有源区的一端连接到第一栅极布线，另一端包括 第一突出部分在与第一有源区域A的第一栅极布线侧相对的一侧突出。第一NMIS晶体管包括形成在半导体衬底上的具有从第一有源区域剩下的空间的第二有源区和第二栅电极， 形成在所述第二有源区上，并且在其一端连接到所述第一栅极布线，并且在其另一端包括在与所述第二有源区的所述第一栅极布线侧相对的一侧突出的第二突出部。 第一PMIS晶体管的第一突出部分的突出长度大于第一NMIS晶体管的第二突出部分的突出长度。
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7.发明授权Semiconductor device comprising a discontinuous region and/or a continuous region having trench isolation stress applied thereto 失效包括施加到其上的具有沟槽隔离应力的不连续区域和/或连续区域的半导体器件公开(公告)号：US06963115B2
公开(公告)日：2005-11-08
申请号：US10656199
申请日：2003-09-08
IPC分类号： H01L27/08 , H01L21/82 , H01L21/8234 , H01L21/8238 , H01L27/02 , H01L27/088 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823828 , H01L21/823437 , H01L27/0203
摘要： Gates of pMISFETs which need high current driving capability are high-driving-capability gates placed in discontinuous active regions or high-driving-capability gates disposed in two-input active regions. Gate of pMISFETs which do not need high current driving capability are normal gates arranged in continuous active regions. Since the high-driving-capability gates are provided in the discontinuous active regions or the two-input active regions, pMISFETs with high driving capability is achieved by utilizing light holes created due to a lattice distortion.
摘要翻译： 需要高电流驱动能力的pMISFET的栅极是放置在不连续有源区域中的高驱动能力门或设置在双输入有源区域中的高驱动能力门。 不需要高电流驱动能力的pMISFET的栅极是布置在连续有源区域中的常规栅极。 由于高驱动能力门设置在不连续的有源区域或双输入有源区域中，所以通过利用由于晶格畸变而产生的光孔来实现具有高驱动能力的pMISFET。
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公开(公告)号：US07792663B2
公开(公告)日：2010-09-07
申请号：US11822781
申请日：2007-07-10
IPC分类号： G06F17/10
CPC分类号： G06F17/504 , G06F17/5022
摘要： A circuit simulation apparatus has a means to acquire data regarding a transistor, a model parameter generation unit for generating a model parameter representing effects of stress upon the transistor active region caused by the isolation region, and a simulation execution unit for evaluating characteristics of the transistor using a simulation program associated with the model parameter. The model parameter includes a term regarding width of the transistor active region, a term regarding width of the peripheral active region, and a term regarding width between the transistor active region and the peripheral active region.
摘要翻译： 电路模拟装置具有获取关于晶体管的数据的模块，用于产生表示由隔离区域引起的晶体管有源区上的应力的影响的模型参数的模型参数生成单元，以及用于评估晶体管的特性的模拟执行单元 使用与模型参数相关联的模拟程序。 模型参数包括关于晶体管有源区的宽度的术语，关于外围有源区的宽度的术语，以及关于晶体管有源区和外围有源区之间的宽度的项。
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公开(公告)号：US07562327B2
公开(公告)日：2009-07-14
申请号：US11591452
申请日：2006-11-02
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , H01L21/823878 , H01L21/823892 , H01L29/41758
摘要： In a cell comprising an N well and a P well, a distance SP04 from a center line of a contact N-type region to an N well end of the N well is set to be a distance which causes a transistor not to be affected by resist. A distance from a well boundary to the center line of the contact N-type region is equal to SP04. A design on the P well is similar to that on the N well. Thereby, modeling of the transistor in the cell can be performed, taking into consideration an influence from resist in one direction. Also, by fabricating a cell array which satisfies the above-described conditions, design accuracy can be improved.
摘要翻译： 在包括N阱和P阱的单元中，从接触N型区域的中心线到N阱的N阱端的距离SP04被设定为使晶体管不受影响的距离 抗。 从阱边界到接触N型区域的中心线的距离等于SP04。 P井的设计与N井相似。 因此，考虑到在一个方向上的抗蚀剂的影响，可以对单元中的晶体管进行建模。 此外，通过制造满足上述条件的单元阵列，可以提高设计精度。
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公开(公告)号：US20070141766A1
公开(公告)日：2007-06-21
申请号：US11591452
申请日：2006-11-02
IPC分类号： H01L21/84
CPC分类号： H01L27/0207 , H01L21/823878 , H01L21/823892 , H01L29/41758
摘要： In a cell comprising an N well and a P well, a distance SP04 from a center line of a contact N-type region to an N well end of the N well is set to be a distance which causes a transistor not to be affected by resist. A distance from a well boundary to the center line of the contact N-type region is equal to SP04. A design on the P well is similar to that on the N well. Thereby, modeling of the transistor in the cell can be performed, taking into consideration an influence from resist in one direction. Also, by fabricating a cell array which satisfies the above-described conditions, design accuracy can be improved.
摘要翻译： 在包括N阱和P阱的单元中，从接触N型区域的中心线到N阱的N阱端的距离SP 04被设定为使晶体管不受影响的距离 抗拒。 从触点N型区域的阱边界到中心线的距离等于SP 04。 P井的设计与N井相似。 因此，考虑到在一个方向上的抗蚀剂的影响，可以对单元中的晶体管进行建模。 此外，通过制造满足上述条件的单元阵列，可以提高设计精度。
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