Method And Apparatus For Seasoning Semiconductor Apparatus Of Sensing Plasma Equipment
    1.
    发明申请
    Method And Apparatus For Seasoning Semiconductor Apparatus Of Sensing Plasma Equipment 审中-公开
    感应等离子体设备调味半导体装置的方法和装置

    公开(公告)号:US20070201016A1

    公开(公告)日:2007-08-30

    申请号:US10584108

    申请日:2004-12-21

    IPC分类号: G01N21/00

    摘要: A plasma equipment seasoning method. The seasoning method comprising the steps of measuring the ratio of optical emission intensity of silicon oxide (SiOx)-based chemical species to optical emission intensity of carbon fluoride compound (CFy)-based chemical species present in a process chamber of plasma equipment before operating the plasma equipment to perform a plasma process, determining whether the value of the measured optical emission intensity ratio is within a predetermined range of normal state or not, and, when reaction gas to be used in the plasma process is supplied into the process chamber based on the result of determination such that the value of the measured optical emission intensity ratio is within the predetermined range of normal state, seasoning the interior of the process chamber to change the ratio of components of the reaction gas, and thus, to change the optical emission intensity ratio.

    摘要翻译: 等离子设备调味方法。 该调味方法包括以下步骤:测量基于氧化硅(SiO 2)的化学物质的光发射强度与氟化碳化合物的光发射强度的比率(CF )的等离子体设备的处理室中存在的化学物质,然后操作等离子体设备以执行等离子体处理,确定测量的光发射强度比值是否在正常状态的预定范围内,以及当反应 基于测定结果将等离子体处理中使用的气体供给到处理室,使得测定的发光强度比值在正常状态的预定范围内,调节处理室的内部以改变 反应气体成分的比例,从而改变光发射强度比。

    Method of manufacturing flash memory device
    2.
    发明申请
    Method of manufacturing flash memory device 审中-公开
    制造闪存设备的方法

    公开(公告)号:US20070004141A1

    公开(公告)日:2007-01-04

    申请号:US11479285

    申请日:2006-06-30

    申请人: Nam Kim Eun Choi Sang Oh

    发明人: Nam Kim Eun Choi Sang Oh

    IPC分类号: H01L21/336

    摘要: A method of manufacturing a flash memory device which can improve capacitance and can reduce the interference phenomenon. According to one embodiment, a method of manufacturing a flash memory device includes the steps of depositing a tunnel oxide layer over a semiconductor substrate having a isolation structure, depositing a conductive layers for a floating gate over the tunnel oxide layer, forming an oxide layer between the conductive layers for the floating gate, forming a recess pattern in the conductive layers for the floating gate, and depositing a dielectric layer and a conductive layer for a control gate, respectively.

    摘要翻译: 一种可以改善电容并可以减少干扰现象的闪速存储器件的制造方法。 根据一个实施例,一种制造闪速存储器件的方法包括以下步骤:在具有隔离结构的半导体衬底上沉积隧道氧化物层,在隧道氧化物层之上沉积用于浮置栅极的导电层,在隧道氧化物层之间形成氧化物层 用于浮置栅极的导电层,在用于浮置栅极的导电层中形成凹陷图案,以及分别为控制栅极沉积介电层和导电层。

    Electrostatic Chuck And Chuck Base Having Cooling Path For Cooling Wafer
    3.
    发明申请
    Electrostatic Chuck And Chuck Base Having Cooling Path For Cooling Wafer 审中-公开
    静电夹头和卡盘底座具有用于冷却晶片的冷却路径

    公开(公告)号:US20070274020A1

    公开(公告)日:2007-11-29

    申请号:US10583978

    申请日:2004-12-22

    IPC分类号: H01L21/3065

    CPC分类号: H01L21/67109 H01L21/6831

    摘要: The electrostatic chuck comprises a chuck base for supporting a wafer, a dielectric film mounted on the chuck base, the dielectric film having an electrode for supplying direct current voltage to provide an electrostatic force to fix the wafer, the electrode disposed in the dielectric film, and a cooling channel for supplying refrigerant to the dielectric film to control the temperature of the wafer. At least two first cooling channel parts are formed at the surface of the dielectric film corresponding to the edge part of the wafer such that the first cooling channel parts form concentric circles, second cooling channel parts formed at the surface of the dielectric film such that the first cooling channel parts are connected to each other through the second cooling channel parts, first through channels formed through the dielectric film for supplying the refrigerant to the first and second cooling channel parts, and a second through channel formed through the center of the dielectric film for supplying the refrigerant to the center of the wafer.

    摘要翻译: 静电卡盘包括用于支撑晶片的卡盘基座,安装在卡盘基座上的电介质膜,该电介质膜具有用于提供直流电压以提供固定晶片的静电力的电极,设置在电介质膜中的电极, 以及用于向电介质膜供给制冷剂以控制晶片的温度的冷却通道。 至少两个第一冷却通道部分形成在对应于晶片的边缘部分的电介质膜的表面上,使得第一冷却通道部分形成同心圆,形成在电介质膜的表面处的第二冷却通道部分使得 第一冷却通道部分通过第二冷却通道部分相互连接,首先通过用于将制冷剂供应到第一和第二冷却通道部分的介电膜形成的通道,以及通过介电膜中心形成的第二通道 用于将制冷剂供应到晶片的中心。

    High Strength Ascon Composition Comprising Slag Ball and Method for Producing the Same
    5.
    发明申请
    High Strength Ascon Composition Comprising Slag Ball and Method for Producing the Same 审中-公开
    包含炉渣球的高强度Ascon组合物及其生产方法

    公开(公告)号:US20070240611A1

    公开(公告)日:2007-10-18

    申请号:US11579841

    申请日:2005-05-04

    申请人: Ok-Soo Oh Sang Oh

    发明人: Ok-Soo Oh Sang Oh

    IPC分类号: C04B18/14 C08L95/00

    摘要: Provided are ASCON utilizing atomized slag as fine aggregates and a method for producing the same. More particularly, provided are ASCON composition that is improved in strength by substituting all or part of fine aggregates for atomized slag and a method for producing the same. ASCON composition includes coarse aggregates, fine aggregates, fillers, and asphalt. When the fine aggregates is 100 parts by weight, the fine aggregates include 0-70 parts by weight of atomized slag balls having a diameter of less than 5mm. Accordingly, it is possible to obtain the ASCON composition that has large strength and can greatly reduce a heating temperature in the mixing operation.

    摘要翻译: 提供了使用雾化炉渣作为细骨料的ASCON及其制造方法。 更具体地,提供了通过用全部或部分细粒子代替雾化炉渣来提高强度的ASCON组合物及其制备方法。 ASCON组合物包括粗骨料,细骨料,填料和沥青。 当细骨料为100重量份时,细骨料包括0-70重量份直径小于5mm的雾化球渣。 因此,可以获得强度高且可以大大降低混合操作中的加热温度的ASCON组合物。

    Cell string of flash memory device and method of manufacturing the same
    6.
    发明申请
    Cell string of flash memory device and method of manufacturing the same 审中-公开
    闪存设备的单元串及其制造方法

    公开(公告)号:US20070064496A1

    公开(公告)日:2007-03-22

    申请号:US11484437

    申请日:2006-07-11

    申请人: Sang Oh

    发明人: Sang Oh

    IPC分类号: G11C16/04

    摘要: Disclosed herein are a cell string of a flash memory device and a method of manufacturing the same. The cell string of a flash memory device includes a plurality of memory cells connected to a single bit line and arranged with first distance between the memory cells, and a source select transistor connected to a common source region and having the second distance between the source select transistor and the first memory cell of the plurality of memory cells. The second distance is greater than the first distance and less than three times of the first distance.

    摘要翻译: 这里公开了闪速存储器件的单元串及其制造方法。 闪速存储器件的单元串包括连接到单个位线并且以存储单元之间的第一距离布置的多个存储器单元,以及连接到公共源极区域并且具有源极选择之间的第二距离的源极选择晶体管 晶体管和多个存储单元中的第一存储单元。 第二距离大于第一距离,小于第一距离的三倍。