公开(公告)号：US06570917B1

公开(公告)日：2003-05-27

申请号：US09338664

申请日：1999-06-22

申请人： Yhean-Sen Lai ,  Zhenyu Wang ,  Jiangtao Xi ,  Bahman Barazesh

发明人： Yhean-Sen Lai ,  Zhenyu Wang ,  Jiangtao Xi ,  Bahman Barazesh

IPC分类号： H03K5159

CPC分类号： H04L5/143 ,  H04L25/03146 ,  H04L25/4927 ,  H04L2025/03363 ,  H04L2025/0349 ,  H04L2025/03503 ,  H04L2025/0377 ,  H04L2025/03783

摘要： Analog modems are enabled to better learn the slicing levels employed at the interface to a digital transmission network by reducing the effects of the various noise sources. Initially a training sequence is received to preliminarily adjust the analog modem's equalizer. Thereafter, a special training sequence, protected against intersymbol interference, is employed to collect samples of each slicing level, to ascertain the least mean squared value of each slicing level from the received samples and to obtain the channel's impulse response at each slicing level. To mitigate the effects of robbed bit signaling that may be employed in the digital transmission network, an array of slicers is provided to determine which bit position is being robbed and to base level learning on samples obtained from the non-robbed positions.

摘要翻译： 使模拟调制解调器能够通过减少各种噪声源的影响，更好地了解在数字传输网络的接口处采用的切片级别。 最初接收训练序列以初步调整模拟调制解调器的均衡器。 此后，采用保护码间干扰的特殊训练序列来收集每个限幅电平的样本，以便从接收到的采样中确定每个限幅电平的最小均方值，并在每个限幅电平下获得信道的脉冲响应。 为了减轻可能在数字传输网络中使用的抢占位信令的影响，提供了一系列限幅器，以确定哪个位位置被抢走，并从非抢占位置获得的样本的基础级学习。

公开(公告)号：US06600780B1

公开(公告)日：2003-07-29

申请号：US09338134

申请日：1999-06-22

申请人： Zhenyu Wang ,  Yhean-Sen Lai ,  Jiangtao Xi ,  Bahman Barazesh

发明人： Zhenyu Wang ,  Yhean-Sen Lai ,  Jiangtao Xi ,  Bahman Barazesh

IPC分类号： H03H2100

CPC分类号： H04L25/03146 ,  H04L5/143 ,  H04L25/4927 ,  H04L2025/03503 ,  H04L2025/0377

摘要： Analog modems are enabled to better learn the slicing levels employed at the interface to a digital transmission network by reducing the effects of the various noise sources. Initially a training sequence is received to preliminarily adjust the analog modem's equalizer. Thereafter, a special training sequence, protected against intersymbol interference, is employed to collect samples of each slicing level, to ascertain the least mean squared value of each slicing level from the received samples and to obtain the channel's impulse response at each slicing level. Depending on the means squared error (MSE) between the input and the output of the slicer, the slicer tables continue to be updated, and the feed-forward and feed-backward equalizer filters are selectively adjusted in accordance with the channel impulse response ascertained at each of the slicing levels.

摘要翻译： 使模拟调制解调器能够通过减少各种噪声源的影响，更好地了解在数字传输网络的接口处采用的切片级别。 最初接收训练序列以初步调整模拟调制解调器的均衡器。 此后，采用保护码间干扰的特殊训练序列来收集每个限幅电平的样本，以便从接收到的采样中确定每个限幅电平的最小均方值，并在每个限幅电平下获得信道的脉冲响应。 根据切片器的输入和输出之间的均方误差（MSE），切片器表继续更新，并且前馈和反馈均衡器滤波器根据在 每个切片级别。

公开(公告)号：US06185250B2

公开(公告)日：2001-02-06

申请号：US09337687

申请日：1999-06-22

申请人： Zhenyu Wang ,  Yhean-Sen Lai ,  Jiangtao Xi ,  Bahman Barazesh

发明人： Zhenyu Wang ,  Yhean-Sen Lai ,  Jiangtao Xi ,  Bahman Barazesh

IPC分类号： H04B138

CPC分类号： H04L25/4927 ,  H04L5/143 ,  H04L25/03146 ,  H04L2025/03363 ,  H04L2025/0349 ,  H04L2025/03503 ,  H04L2025/0377 ,  H04L2025/03783

摘要： Analog modems are enabled to better learn the slicing levels employed at the interface to a digital transmission network by reducing the effects of the various noise sources. Initially a training sequence is received to preliminarily adjust the analog modem's equalizer. Thereafter, a special training sequence, protected against intersymbol interference, is employed to collect samples of each slicing level, to ascertain the least mean squared value of each slicing level from the received samples and to obtain the channel's impulse response at each slicing level. Thereafter, the analog modem's equalizer may be fine tuned in accordance with the channel impulse response ascertained at each slicing level.

摘要翻译： 使模拟调制解调器能够通过减少各种噪声源的影响，更好地了解在数字传输网络的接口处采用的切片级别。 最初接收训练序列以初步调整模拟调制解调器的均衡器。 此后，采用保护码间干扰的特殊训练序列来收集每个限幅电平的样本，以便从接收到的采样中确定每个限幅电平的最小均方值，并在每个限幅电平下获得信道的脉冲响应。 此后，模拟调制解调器的均衡器可以根据在每个切片级别确定的信道脉冲响应进行微调。

公开(公告)号：US06771695B1

公开(公告)日：2004-08-03

申请号：US09364411

申请日：1999-07-30

申请人： Raja Banerjea ,  Bahman Barazesh ,  Yhean-Sen Lai ,  Kannan Rajamani ,  Geoffrey L. Smith

发明人： Raja Banerjea ,  Bahman Barazesh ,  Yhean-Sen Lai ,  Kannan Rajamani ,  Geoffrey L. Smith

IPC分类号： H04B138

CPC分类号： H04L25/05 ,  H04L27/2608

摘要： A DMT signal conforming to a first DMT standard (e.g., the full-rate G.dmt standard based on 255 tones) is sampled at a sampling rate for the first DMT standard, filtered to attenuate a subset of the tones of the first DMT standard (e.g., all G.dmt tones above tone #127), and subsampled (e.g., 2:1) to provide a subsampled, filtered signal that can be further processed using components designed to operate under a second, different DMT standard (e.g., the half-rate G.lite standard based on 127 tones). As such, a conventional half-rate G.lite DMT transceiver can be modified (e.g., by changing the downstream sampling rate from 1.104 MHz to 2.208 MHz and adding an appropriate low-pass filter and decimator) for configuration in a full-rate G.dmt DMT system. The filtering and subsampling ensure that a downstream signal (even if it is a full-rate DMT initialization or synchronization signal containing tones above tone #127) can successfully be further processed using conventional half-rate DMT transceiver components, which are less complex and less expensive than those of full-rate DMT transceivers, thereby enabling the use of relatively inexpensive consumer personal equipment (CPE) in existing distributed full-rate DMT telecommunications systems.

摘要翻译： 符合第一DMT标准（例如，基于255个音调的全速率G.dmt标准）的DMT信号以对于第一DMT标准的采样率进行采样，被滤波以衰减第一DMT标准的音调的子集 （例如，音调＃127之上的所有G.dmt音调），并且被二次采样（例如，2:1）以提供可以使用被设计为在第二种不同DMT标准下操作的组件进一步处理的子采样滤波信号（例如， 基于127个音调的半速率G.lite标准）。 因此，传统的半速率G.lite DMT收发器可以被修改（例如，通过将下行采样率从1.104MHz改变到2.208MHz并添加适当的低通滤波器和抽取器）来配置全速率G .dmt DMT系统。 滤波和二次采样确保下行信号（即使是全速率DMT初始化或包含音调＃127以上的音频的同步信号）也可以使用传统的半速率DMT收发器组件进行进一步处理，这些组件不太复杂和较少 比全速率DMT收发器更昂贵，从而能够在现有的分布式全速率DMT电信系统中使用相对便宜的消费者个人设备（CPE）。

公开(公告)号：US06240128B1

公开(公告)日：2001-05-29

申请号：US09096425

申请日：1998-06-11

申请人： Raja Banerjea ,  Bahman Barazesh ,  Yhean-Sen Lai ,  Kannan Rajamani

发明人： Raja Banerjea ,  Bahman Barazesh ,  Yhean-Sen Lai ,  Kannan Rajamani

IPC分类号： H04L516

CPC分类号： H04B3/23 ,  H04L5/16

摘要： A so-called post equalization echo canceler is utilized in conjunction with transmitter and receiver data timing synchronization to enhance tracking of the echo path impulse response and convergence of the transversal filter in the post equalization echo canceler. This is realized by employing the equalization error in the receiver to adapt coefficients of the post equalization echo canceler transversal filter, in conjunction, with the transmitter and receiver data timing synchronization. The timing synchronization is realized by using sample rate conversion of the transmit sample rate to the receive sample rate and, in one example, variable phase interpolation of the converted timing signal. The receiver timing is recovered, and a phase error signal generated by the timing recovery unit is advantageously employed to adjust a variable phase interpolator in the receiver and a variable phase interpolator in a path supplying the transmitter signal to an input of the post equalization echo canceler. This insures that both the adaptive transversal filter of the post equalization echo canceler and a transversal filter in an equalizer in the receiver are operating on data having the same timing. In this example, the timing is that of the received data signal. In an embodiment of the invention, the post equalization echo canceler is utilized in conjunction with a so-called conventional, e.g., a primary, echo canceler. The conventional echo canceler is employed before the equalizer to cancel a major portion of any echo signal, while the post equalization echo canceler is employed after the equalizer to cancel residual echo signals caused primarily by drift in the hybrid network. To this end, the conventional echo canceler is “trained” during the initial half-duplex operation of the modem and, then, updating of its impulse response is inhibited, while the post equalization echo canceler is allowed to continue adapting.

摘要翻译： 所谓后置均衡回波消除器与发射机和接收机数据定时同步结合使用，以增强跟踪均衡回波消除器中的回波路径脉冲响应和横向滤波器的收敛。 这通过在接收机中采用均衡误差来实现，以使后均衡回波消除器横向滤波器的系数与发射机和接收机的数据定时同步相结合。 通过使用发送采样率的采样率转换为接收采样率，并且在一个示例中，转换的定时信号的可变相位插值来实现定时同步。 接收器定时被恢复，并且有利地采用由定时恢复单元产生的相位误差信号来调整接收机中的可变相位内插器和将发射机信号提供给后均衡回波消除器的输入的路径中的可变相位内插器 。 这确保后均衡回波消除器的自适应横向滤波器和接收机中的均衡器中的横向滤波器对具有相同定时的数据进行操作。 在该示例中，定时是所接收的数据信号的时序。 在本发明的一个实施例中，后均衡回波消除器与所谓常规的，例如主回波消除器结合使用。 在均衡器之前采用传统的回波消除器来消除任何回波信号的主要部分，而在均衡器之后采用后均衡回波消除器来消除主要由混合网络中的漂移引起的残余回波信号。 为此，传统的回波消除器在调制解调器的初始半双工操作期间被“训练”，然后，抑制其脉冲响应的更新，同时允许后均衡回波消除器继续适配。

公开(公告)号：US6128370A

公开(公告)日：2000-10-03

申请号：US906818

申请日：1997-08-06

申请人： Bahman Barazesh ,  Sherry Shuihong Zhu

发明人： Bahman Barazesh ,  Sherry Shuihong Zhu

IPC分类号： H04M1/00 ,  H04M1/24

CPC分类号： H04M1/82 ,  H04Q1/457

摘要： A multiple tone detector includes n tone detectors, each detecting one of n distinct tones, where n.gtoreq.2, and a background detector which generates a measure of accumulative background energy E.sub.avg in a frequency band or bands which do not include at least a subset of the n tones. The output of the background detector is applied to a smoothing filter, which generates the accumulative background energy measure E.sub.avg for a current frame as a weighted sum of the background detector output for the current frame and the background energy measure E.sub.avg from a previous frame. A parameter controlling response time of the smoothing filter is varied depending upon whether or not speech is determined to be present in the background portion of the input signal. A processor uses the energy measures from the n tone detectors and the background detector to compute n ratios, where a given ratio is the ratio of the energy measure of the ith tone to the accumulative background energy measure E.sub.avg. The processor determines if each of the n ratios are greater than a threshold, and if the maximum of the n ratios is less than a constant times the minimum of the n ratios, in order to generate a decision as to whether the n tones are present in the input signal.

摘要翻译： 多重色调检测器包括n个音调检测器，每个检测器检测n个不同音调中的一个，其中n≥2;以及背景检测器，其产生频带或频带中的累积背景能量Eavg的量度，其不包括至少一个 n个音调的子集。 背景检测器的输出被应用于平滑滤波器，其产生当前帧的累加背景能量测量Eavg作为当前帧的背景检测器输出和来自前一帧的背景能量测量Eavg的加权和。 根据是否确定语音在输入信号的背景部分中存在，来调整平滑滤波器的响应时间的参数。 处理器使用来自n个音调检测器和背景检测器的能量测量来计算n个比率，其中给定的比率是第i个音调的能量测量与累积背景能量测量Eavg的比率。 处理器确定n个比率中的每一个是否大于阈值，并且如果n个比率的最大值小于n个比率的最小值的常数，则为了产生n个音调是否存在的决定 在输入信号中。

公开(公告)号：US4845660A

公开(公告)日：1989-07-04

申请号：US161340

申请日：1988-02-19

申请人： Mary Luc ,  Bahman Barazesh

发明人： Mary Luc ,  Bahman Barazesh

IPC分类号： G06F15/167 ,  G06F15/17 ,  G06F15/78

CPC分类号： G06F15/17 ,  G06F15/7832

摘要： A processor formed from a signal processing unit operating according to instructions transmitted by a bus line, including a slave section provided with an address/data port for connection to a master signal processing circuit; a first buffer register in which data coming from the master processing circuit via the address/data port can be written and read in order to be processed by the processing unit, a second buffer register in which the data processed by the processing unit can be written, then read in order to be directed via the address/data port to the master processing circuit and a sequential control circuit so that access to these buffer registers is allocated in turn to the processing unit and to the master processing circuit. A master section is also provided intended to be connected to at least one slave circuit.

摘要翻译： 由根据由总线发送的指令进行操作的信号处理单元构成的处理器，包括：具有与主信号处理电路连接的地址/数据端口的从单元; 第一缓冲寄存器，其中可以写入和读取来自主处理电路的经由地址/数据端口的数据，以便由处理单元处理;第二缓冲寄存器，其中可以写入由处理单元处理的数据 然后读取以便通过地址/数据端口被引导到主处理电路和顺序控制电路，使得对这些缓冲寄存器的访问依次分配给处理单元和主处理电路。 还提供了要被连接到至少一个从属电路的主部分。

公开(公告)号：US06873650B1

公开(公告)日：2005-03-29

申请号：US09607619

申请日：2000-06-30

申请人： Raja Banerjea ,  Bahman Barazesh ,  Tony S. El-Kik ,  Kannan Rajamani

发明人： Raja Banerjea ,  Bahman Barazesh ,  Tony S. El-Kik ,  Kannan Rajamani

IPC分类号： H04B1/38 ,  H04J3/16 ,  H04L27/26

CPC分类号： H04L27/2608

摘要： A circuit compensating for the difference in transmission rate of digital samples generated in transmit and receive paths between a user and a transceiver processing in the frequency domain, such as a digital multi-tone (DMT) transceiver. Compensation of the DMT transmission rate in the receive path in accordance with exemplary embodiments of the present employs zero-padding of the frequency domain coefficients generated by the DMT transceiver prior to applying an inverse transform, such as the inverse fast Fourier transform (IFFT). Zero-padding the frequency domain coefficients allows for the compensation of the transmission rate in the receive path by generating digital samples from the frequency domain coefficients with an inverse transform having a rate matched to the frequency domain transform and rate employed in the transmit path.

摘要翻译： 补偿在用户与频域中的收发器处理（例如数字多音调（DMT）收发器）之间的发送和接收路径中产生的数字样本的传输速率差异的电路。 根据本发明的示例性实施例，在接收路径中的DMT传输速率的补偿在应用诸如快速傅里叶逆变换（IFFT）的逆变换之前，由DMT收发器产生的频域系数的零填充。 对频域系数进行零填充允许通过利用与发送路径中采用的频域变换和速率匹配的速率的逆变换从频域系数生成数字样本来补偿接收路径中的传输速率。

公开(公告)号：US4792892A

公开(公告)日：1988-12-20

申请号：US48481

申请日：1987-05-01

申请人： Luc Mary ,  Bahman Barazesh

发明人： Luc Mary ,  Bahman Barazesh

IPC分类号： G06F9/38 ,  G06F9/32 ,  G06F9/42 ,  G06F9/40

CPC分类号： G06F9/4426 ,  G06F9/325

摘要： A data processor for executing a program of instructions stored in a program memory controlled by a program counter. To execute a loop control instruction, calling for repeated execution N times of a sequence of "i" instructions, the processor includes a loop circuit having an instruction counter which counts execution of the instructions in the loop sequence and produces an end-of-sequence signal upon each completion of the loop, a register which refreshes the program counter with the address of the first instruction in the loop in response to each end-of-sequence signal, and a loop counter which counts the number of completions of the loop and delivers a signal indicating the end of the loop portion of the entire program and enabling the program counter to continue on with the rest of the program. The delay in loop execution permits initializing of registers in the data processor so as to permit pipeline execution of the loop instruction.

摘要翻译： 一种用于执行存储在由程序计数器控制的程序存储器中的指令程序的数据处理器。 为了执行循环控制指令，呼叫重复执行“I”个指令序列的N次，处理器包括一个循环电路，该循环电路具有计数循环序列中指令的执行并产生序列结束的指令计数器 每循环结束时产生一个寄存器，该寄存器响应于每个结束序列信号，用循环中的第一个指令的地址刷新程序计数器，以及循环计数器，其对循环的完成次数进行计数， 传递指示整个程序的循环部分结束的信号，并使程序计数器能够继续执行程序的其余部分。 循环执行的延迟允许初始化数据处理器中的寄存器，以允许流水线执行循环指令。

公开(公告)号：US4755965A

公开(公告)日：1988-07-05

申请号：US765020

申请日：1985-08-12

申请人： Luc Mary ,  Bahman Barazesh

发明人： Luc Mary ,  Bahman Barazesh

IPC分类号： G06F7/38 ,  G06F7/00 ,  G06F7/48 ,  G06F7/508 ,  G06F7/52 ,  G06F7/527 ,  G06F7/544 ,  G06F7/57 ,  G06F7/76 ,  G06F9/30 ,  G06F9/305 ,  G06F9/318 ,  G06F17/16 ,  G06F9/00

CPC分类号： G06F7/5324 ,  G06F7/4812 ,  G06F7/5443 ,  G06F7/57 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30189 ,  G06F2207/3828 ,  G06F2207/3884

摘要： A processor for carrying out a calculation mode from a selected plurality of different modes. The processor includes a clock pulse generator which generates clock pulses in an order for processing subsequent data. A mode circuit is included for detecting a mode declaration instruction. The mode declaration instruction is decoded to select a different clock pulse cycle for each different mode selected. Mode control signals and the selected clock pulse cycle are applied to a control code and borrow management circuit to enable the arithmetic and logic unit to carry out one or more operations of the mode control signals.

摘要翻译： 一种用于从所选择的多种不同模式中执行计算模式的处理器。 该处理器包括一个时钟脉冲发生器，其按照处理后续数据的顺序产生时钟脉冲。 包括用于检测模式声明指令的模式电路。 模式声明指令被解码以针对所选择的每个不同模式选择不同的时钟脉冲周期。 模式控制信号和所选择的时钟脉冲周期被施加到控制代码和借位管理电路，以使得算术和逻辑单元能够执行模式控制信号的一个或多个操作。