公开(公告)号：US6128370A

公开(公告)日：2000-10-03

申请号：US906818

申请日：1997-08-06

申请人： Bahman Barazesh ,  Sherry Shuihong Zhu

发明人： Bahman Barazesh ,  Sherry Shuihong Zhu

IPC分类号： H04M1/00 ,  H04M1/24

CPC分类号： H04M1/82 ,  H04Q1/457

摘要： A multiple tone detector includes n tone detectors, each detecting one of n distinct tones, where n.gtoreq.2, and a background detector which generates a measure of accumulative background energy E.sub.avg in a frequency band or bands which do not include at least a subset of the n tones. The output of the background detector is applied to a smoothing filter, which generates the accumulative background energy measure E.sub.avg for a current frame as a weighted sum of the background detector output for the current frame and the background energy measure E.sub.avg from a previous frame. A parameter controlling response time of the smoothing filter is varied depending upon whether or not speech is determined to be present in the background portion of the input signal. A processor uses the energy measures from the n tone detectors and the background detector to compute n ratios, where a given ratio is the ratio of the energy measure of the ith tone to the accumulative background energy measure E.sub.avg. The processor determines if each of the n ratios are greater than a threshold, and if the maximum of the n ratios is less than a constant times the minimum of the n ratios, in order to generate a decision as to whether the n tones are present in the input signal.

摘要翻译： 多重色调检测器包括n个音调检测器，每个检测器检测n个不同音调中的一个，其中n≥2;以及背景检测器，其产生频带或频带中的累积背景能量Eavg的量度，其不包括至少一个 n个音调的子集。 背景检测器的输出被应用于平滑滤波器，其产生当前帧的累加背景能量测量Eavg作为当前帧的背景检测器输出和来自前一帧的背景能量测量Eavg的加权和。 根据是否确定语音在输入信号的背景部分中存在，来调整平滑滤波器的响应时间的参数。 处理器使用来自n个音调检测器和背景检测器的能量测量来计算n个比率，其中给定的比率是第i个音调的能量测量与累积背景能量测量Eavg的比率。 处理器确定n个比率中的每一个是否大于阈值，并且如果n个比率的最大值小于n个比率的最小值的常数，则为了产生n个音调是否存在的决定 在输入信号中。

公开(公告)号：US4845660A

公开(公告)日：1989-07-04

申请号：US161340

申请日：1988-02-19

申请人： Mary Luc ,  Bahman Barazesh

发明人： Mary Luc ,  Bahman Barazesh

IPC分类号： G06F15/167 ,  G06F15/17 ,  G06F15/78

CPC分类号： G06F15/17 ,  G06F15/7832

摘要： A processor formed from a signal processing unit operating according to instructions transmitted by a bus line, including a slave section provided with an address/data port for connection to a master signal processing circuit; a first buffer register in which data coming from the master processing circuit via the address/data port can be written and read in order to be processed by the processing unit, a second buffer register in which the data processed by the processing unit can be written, then read in order to be directed via the address/data port to the master processing circuit and a sequential control circuit so that access to these buffer registers is allocated in turn to the processing unit and to the master processing circuit. A master section is also provided intended to be connected to at least one slave circuit.

摘要翻译： 由根据由总线发送的指令进行操作的信号处理单元构成的处理器，包括：具有与主信号处理电路连接的地址/数据端口的从单元; 第一缓冲寄存器，其中可以写入和读取来自主处理电路的经由地址/数据端口的数据，以便由处理单元处理;第二缓冲寄存器，其中可以写入由处理单元处理的数据 然后读取以便通过地址/数据端口被引导到主处理电路和顺序控制电路，使得对这些缓冲寄存器的访问依次分配给处理单元和主处理电路。 还提供了要被连接到至少一个从属电路的主部分。

公开(公告)号：US06570917B1

公开(公告)日：2003-05-27

申请号：US09338664

申请日：1999-06-22

申请人： Yhean-Sen Lai ,  Zhenyu Wang ,  Jiangtao Xi ,  Bahman Barazesh

发明人： Yhean-Sen Lai ,  Zhenyu Wang ,  Jiangtao Xi ,  Bahman Barazesh

IPC分类号： H03K5159

CPC分类号： H04L5/143 ,  H04L25/03146 ,  H04L25/4927 ,  H04L2025/03363 ,  H04L2025/0349 ,  H04L2025/03503 ,  H04L2025/0377 ,  H04L2025/03783

摘要： Analog modems are enabled to better learn the slicing levels employed at the interface to a digital transmission network by reducing the effects of the various noise sources. Initially a training sequence is received to preliminarily adjust the analog modem's equalizer. Thereafter, a special training sequence, protected against intersymbol interference, is employed to collect samples of each slicing level, to ascertain the least mean squared value of each slicing level from the received samples and to obtain the channel's impulse response at each slicing level. To mitigate the effects of robbed bit signaling that may be employed in the digital transmission network, an array of slicers is provided to determine which bit position is being robbed and to base level learning on samples obtained from the non-robbed positions.

摘要翻译： 使模拟调制解调器能够通过减少各种噪声源的影响，更好地了解在数字传输网络的接口处采用的切片级别。 最初接收训练序列以初步调整模拟调制解调器的均衡器。 此后，采用保护码间干扰的特殊训练序列来收集每个限幅电平的样本，以便从接收到的采样中确定每个限幅电平的最小均方值，并在每个限幅电平下获得信道的脉冲响应。 为了减轻可能在数字传输网络中使用的抢占位信令的影响，提供了一系列限幅器，以确定哪个位位置被抢走，并从非抢占位置获得的样本的基础级学习。

公开(公告)号：US4755965A

公开(公告)日：1988-07-05

申请号：US765020

申请日：1985-08-12

申请人： Luc Mary ,  Bahman Barazesh

发明人： Luc Mary ,  Bahman Barazesh

IPC分类号： G06F7/38 ,  G06F7/00 ,  G06F7/48 ,  G06F7/508 ,  G06F7/52 ,  G06F7/527 ,  G06F7/544 ,  G06F7/57 ,  G06F7/76 ,  G06F9/30 ,  G06F9/305 ,  G06F9/318 ,  G06F17/16 ,  G06F9/00

CPC分类号： G06F7/5324 ,  G06F7/4812 ,  G06F7/5443 ,  G06F7/57 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30189 ,  G06F2207/3828 ,  G06F2207/3884

摘要： A processor for carrying out a calculation mode from a selected plurality of different modes. The processor includes a clock pulse generator which generates clock pulses in an order for processing subsequent data. A mode circuit is included for detecting a mode declaration instruction. The mode declaration instruction is decoded to select a different clock pulse cycle for each different mode selected. Mode control signals and the selected clock pulse cycle are applied to a control code and borrow management circuit to enable the arithmetic and logic unit to carry out one or more operations of the mode control signals.

摘要翻译： 一种用于从所选择的多种不同模式中执行计算模式的处理器。 该处理器包括一个时钟脉冲发生器，其按照处理后续数据的顺序产生时钟脉冲。 包括用于检测模式声明指令的模式电路。 模式声明指令被解码以针对所选择的每个不同模式选择不同的时钟脉冲周期。 模式控制信号和所选择的时钟脉冲周期被施加到控制代码和借位管理电路，以使得算术和逻辑单元能够执行模式控制信号的一个或多个操作。

公开(公告)号：US06873650B1

公开(公告)日：2005-03-29

申请号：US09607619

申请日：2000-06-30

申请人： Raja Banerjea ,  Bahman Barazesh ,  Tony S. El-Kik ,  Kannan Rajamani

发明人： Raja Banerjea ,  Bahman Barazesh ,  Tony S. El-Kik ,  Kannan Rajamani

IPC分类号： H04B1/38 ,  H04J3/16 ,  H04L27/26

CPC分类号： H04L27/2608

摘要： A circuit compensating for the difference in transmission rate of digital samples generated in transmit and receive paths between a user and a transceiver processing in the frequency domain, such as a digital multi-tone (DMT) transceiver. Compensation of the DMT transmission rate in the receive path in accordance with exemplary embodiments of the present employs zero-padding of the frequency domain coefficients generated by the DMT transceiver prior to applying an inverse transform, such as the inverse fast Fourier transform (IFFT). Zero-padding the frequency domain coefficients allows for the compensation of the transmission rate in the receive path by generating digital samples from the frequency domain coefficients with an inverse transform having a rate matched to the frequency domain transform and rate employed in the transmit path.

摘要翻译： 补偿在用户与频域中的收发器处理（例如数字多音调（DMT）收发器）之间的发送和接收路径中产生的数字样本的传输速率差异的电路。 根据本发明的示例性实施例，在接收路径中的DMT传输速率的补偿在应用诸如快速傅里叶逆变换（IFFT）的逆变换之前，由DMT收发器产生的频域系数的零填充。 对频域系数进行零填充允许通过利用与发送路径中采用的频域变换和速率匹配的速率的逆变换从频域系数生成数字样本来补偿接收路径中的传输速率。

公开(公告)号：US4792892A

公开(公告)日：1988-12-20

申请号：US48481

申请日：1987-05-01

申请人： Luc Mary ,  Bahman Barazesh

发明人： Luc Mary ,  Bahman Barazesh

IPC分类号： G06F9/38 ,  G06F9/32 ,  G06F9/42 ,  G06F9/40

CPC分类号： G06F9/4426 ,  G06F9/325

摘要： A data processor for executing a program of instructions stored in a program memory controlled by a program counter. To execute a loop control instruction, calling for repeated execution N times of a sequence of "i" instructions, the processor includes a loop circuit having an instruction counter which counts execution of the instructions in the loop sequence and produces an end-of-sequence signal upon each completion of the loop, a register which refreshes the program counter with the address of the first instruction in the loop in response to each end-of-sequence signal, and a loop counter which counts the number of completions of the loop and delivers a signal indicating the end of the loop portion of the entire program and enabling the program counter to continue on with the rest of the program. The delay in loop execution permits initializing of registers in the data processor so as to permit pipeline execution of the loop instruction.

摘要翻译： 一种用于执行存储在由程序计数器控制的程序存储器中的指令程序的数据处理器。 为了执行循环控制指令，呼叫重复执行“I”个指令序列的N次，处理器包括一个循环电路，该循环电路具有计数循环序列中指令的执行并产生序列结束的指令计数器 每循环结束时产生一个寄存器，该寄存器响应于每个结束序列信号，用循环中的第一个指令的地址刷新程序计数器，以及循环计数器，其对循环的完成次数进行计数， 传递指示整个程序的循环部分结束的信号，并使程序计数器能够继续执行程序的其余部分。 循环执行的延迟允许初始化数据处理器中的寄存器，以允许流水线执行循环指令。

公开(公告)号：US06240128B1

公开(公告)日：2001-05-29

申请号：US09096425

申请日：1998-06-11

申请人： Raja Banerjea ,  Bahman Barazesh ,  Yhean-Sen Lai ,  Kannan Rajamani

发明人： Raja Banerjea ,  Bahman Barazesh ,  Yhean-Sen Lai ,  Kannan Rajamani

IPC分类号： H04L516

CPC分类号： H04B3/23 ,  H04L5/16

摘要： A so-called post equalization echo canceler is utilized in conjunction with transmitter and receiver data timing synchronization to enhance tracking of the echo path impulse response and convergence of the transversal filter in the post equalization echo canceler. This is realized by employing the equalization error in the receiver to adapt coefficients of the post equalization echo canceler transversal filter, in conjunction, with the transmitter and receiver data timing synchronization. The timing synchronization is realized by using sample rate conversion of the transmit sample rate to the receive sample rate and, in one example, variable phase interpolation of the converted timing signal. The receiver timing is recovered, and a phase error signal generated by the timing recovery unit is advantageously employed to adjust a variable phase interpolator in the receiver and a variable phase interpolator in a path supplying the transmitter signal to an input of the post equalization echo canceler. This insures that both the adaptive transversal filter of the post equalization echo canceler and a transversal filter in an equalizer in the receiver are operating on data having the same timing. In this example, the timing is that of the received data signal. In an embodiment of the invention, the post equalization echo canceler is utilized in conjunction with a so-called conventional, e.g., a primary, echo canceler. The conventional echo canceler is employed before the equalizer to cancel a major portion of any echo signal, while the post equalization echo canceler is employed after the equalizer to cancel residual echo signals caused primarily by drift in the hybrid network. To this end, the conventional echo canceler is “trained” during the initial half-duplex operation of the modem and, then, updating of its impulse response is inhibited, while the post equalization echo canceler is allowed to continue adapting.

摘要翻译： 所谓后置均衡回波消除器与发射机和接收机数据定时同步结合使用，以增强跟踪均衡回波消除器中的回波路径脉冲响应和横向滤波器的收敛。 这通过在接收机中采用均衡误差来实现，以使后均衡回波消除器横向滤波器的系数与发射机和接收机的数据定时同步相结合。 通过使用发送采样率的采样率转换为接收采样率，并且在一个示例中，转换的定时信号的可变相位插值来实现定时同步。 接收器定时被恢复，并且有利地采用由定时恢复单元产生的相位误差信号来调整接收机中的可变相位内插器和将发射机信号提供给后均衡回波消除器的输入的路径中的可变相位内插器 。 这确保后均衡回波消除器的自适应横向滤波器和接收机中的均衡器中的横向滤波器对具有相同定时的数据进行操作。 在该示例中，定时是所接收的数据信号的时序。 在本发明的一个实施例中，后均衡回波消除器与所谓常规的，例如主回波消除器结合使用。 在均衡器之前采用传统的回波消除器来消除任何回波信号的主要部分，而在均衡器之后采用后均衡回波消除器来消除主要由混合网络中的漂移引起的残余回波信号。 为此，传统的回波消除器在调制解调器的初始半双工操作期间被“训练”，然后，抑制其脉冲响应的更新，同时允许后均衡回波消除器继续适配。

公开(公告)号：US5953695A

公开(公告)日：1999-09-14

申请号：US959888

申请日：1997-10-29

申请人： Bahman Barazesh ,  San Hyok Yon

发明人： Bahman Barazesh ,  San Hyok Yon

IPC分类号： G10L19/00 ,  G10L3/02 ,  G10L9/00

CPC分类号： G10L19/005

摘要： A digital speech communication system having improved synchronization. The present digital speech communication system reduces the unit of degradation to a single speech sample, rather than a multi-sample frame, while maintaining the bit rate efficiency of the DSVD system and other systems where speech is encoded into large blocks and is subject to variable delay and mismatched clocks. The basic unit that is dropped or artificially inserted by the receiver, if the buffer overflows or empties, respectively, is reduced to a single speech sample. The speech frames produced by the demultiplexer are written into a frame buffer, in units of frames, at a rate determined by the clock signal, S2, that is extracted from the received signal by a timing recovery function in the modem. In accordance with the present invention, the frames are read out of the buffer into the decoder using the same extracted clock signal, S2. In this manner, once the buffer is partially full, the frame buffer will not overflow or empty. The speech decoder converts the coded speech into blocks of speech samples. The blocks of speech samples are then written to a variable frame buffer, in accordance with the extracted clock signal, S2. The variable frame buffer is allowed to partially fill, before the speech samples are read out to the digital-to-analog converter according to a clock signal, S3, at the 8 kHz sample rate, for presentation to the listener. When the variable frame buffer overflows, only a single speech sample needs to be discarded rather than an entire frame of multiple samples. Likewise, when the variable frame buffer empties, only a single extraneous speech sample need be inserted. The number of samples in the variable frame buffer will preferably be kept within predefined tolerances by a write process and a read process.

摘要翻译： 具有改进的同步的数字语音通信系统。 本数字语音通信系统将降级的单位降低到单个语音样本而不是多采样帧，同时保持DSVD系统和其他系统的比特率效率，其中语音被编码成大块并且受到可变 延迟和不匹配的时钟。 接收机丢弃或人为插入的基本单元，如果缓冲区分别溢出或者被清空，则被简化为单个语音样本。 由解复用器产生的语音帧以帧为单位以由调制解调器中的定时恢复功能从接收信号提取的时钟信号S2确定的速率写入帧缓冲器。 根据本发明，使用相同的提取的时钟信号S2将帧从缓冲器中读出到解码器中。 以这种方式，一旦缓冲区部分已满，则帧缓冲区将不会溢出或为空。 语音解码器将编码的语音转换成语音样本块。 然后根据提取的时钟信号S2将语音样本块写入可变帧缓冲器。 在根据时钟信号S3以8kHz采样率将语音样本读出到数模转换器之前，允许可变帧缓冲器部分地填充以呈现给收听者。 当可变帧缓冲器溢出时，只需要丢弃单个语音样本，而不是整个多个样本的帧。 同样，当可变帧缓冲器清空时，只需要插入一个无关的语音样本。 优选地，可变帧缓冲器中的采样数量通过写入处理和读取处理保持在预定义的容限内。

公开(公告)号：US4787065A

公开(公告)日：1988-11-22

申请号：US153526

申请日：1988-02-03

申请人： Bahman Barazesh ,  Luc Mary

发明人： Bahman Barazesh ,  Luc Mary

IPC分类号： G06F7/544 ,  G06F9/355 ,  G06F12/00 ,  G06F12/02 ,  G06F17/10 ,  G11C8/04 ,  H03H17/00 ,  H03H17/04 ,  H03H21/00 ,  G11C7/00 ,  G11C21/00

CPC分类号： G06F9/3552 ,  G06F12/02 ,  G06F7/544 ,  G11C8/04

摘要： A data processing apparatus in which a memory (10) is accessed at addresses stored in an address regiser (20). An incrementation circuit (38) successively increments or decrements the address stored in the principal register, under the control of an address cycling circuit (22). A pair of auxiliary registers (30, 35) respectively store the minimum and maximum address values to be reached in the principal register, and a comparison circuit (37) determines when the address therein matches the minimum or maximum value. The address cycling circuit, together with the comparison circuit, loads the principal register with the minimum address value when the address therein reaches the maximum value, the address therein thereafter being decremented, and loads it with the maximum address value when the address therein reaches the minimum value, the address therein thereafter being incremented. Such operation is particularly useful for preforming the functions of a fixed or adaptive transversal filter for data transmission, the data stored in the memory being the filter coefficients.

摘要翻译： 一种数据处理装置，其中在存储在地址注册器（20）中的地址处访问存储器（10）。 在地址循环电路（22）的控制下，递增电路（38）连续增加或减少存储在主寄存器中的地址。 一对辅助寄存器（30,35）分别存储主寄存器中要达到的最小和最大地址值，并且比较电路（37）确定何时其地址与最小值或最大值匹配。 地址循环电路与比较电路一起，当其中的地址达到最大值时，将主寄存器加载到最小地址值，其中之后的地址递减，并且当其中的地址达到最大地址值时，将其加载到最大地址值 最小值，其中之后的地址增加。 这种操作对于实现用于数据传输的固定或自适应横向滤波器的功能特别有用，存储在存储器中的数据是滤波器系数。

公开(公告)号：US07949723B2

公开(公告)日：2011-05-24

申请号：US10438109

申请日：2003-05-14

申请人： Bahman Barazesh ,  Kannan Rajamani ,  Steven C. Szep ,  Nitin Kumar Varma ,  Tomasz Janusz Wolak

发明人： Bahman Barazesh ,  Kannan Rajamani ,  Steven C. Szep ,  Nitin Kumar Varma ,  Tomasz Janusz Wolak

IPC分类号： G06F15/16

CPC分类号： H04L67/34 ,  H04L69/329 ,  H04M1/24 ,  H04M1/2535

摘要： A unique real time tuning (RTT) process is employed for obtaining the desired optimum device parameter adjustments. The RTT parameter adjustment process is utilized with IP phone or other device chipsets as desired. In one embodiment, RTT provides a graphical user interface to a digital signal processor (DSP), or the like, on the device chipset allowing for observation, evaluation and control of the device parameters in real time. The real time exchange of the device parameter information between the device and an external workstation, e.g., a personal computer or the like, is provided by a User Datagram Protocol (UDP) that runs on a controller on the device, e.g., an ARM processor or the like. In this example, the unique combination of the RTT, UDP and DSP cooperate advantageously to implement, in accordance with the principles of the invention, the desired observability, and control to designers to tune the device, e.g., IP Phone, in real time to specified hardware, plastics, audio requirements required by existing standards or the like.

摘要翻译： 采用独特的实时调谐（RTT）过程来获得所需的最佳设备参数调整。 RTT参数调整过程根据需要与IP电话或其他设备芯片组一起使用。 在一个实施例中，RTT向设备芯片组上的数字信号处理器（DSP）等提供图形用户界面，允许实时观察，评估和控制设备参数。 在设备和外部工作站（例如个人计算机等）之间的设备参数信息的实时交换由在设备上的控制器上运行的用户数据报协议（UDP）提供，例如ARM处理器 或类似物。 在该示例中，RTT，UDP和DSP的独特组合有利地协调，以根据本发明的原理实现期望的可观察性，并且控制设计人员实时调谐设备，例如IP电话， 指定的硬件，塑料，现有标准要求的音频要求等。