公开(公告)号：US06552372B2

公开(公告)日：2003-04-22

申请号：US09827194

申请日：2001-04-05

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen ,  Jian-Ren Shih

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen ,  Jian-Ren Shih

IPC分类号： H01L2972

CPC分类号： H01L27/0251

摘要： An MOS integrated circuit, such as an input-output buffer, exhibits improved resistance to damage from electrostatic discharge (ESD) by balancing the ESD current flow through active and inactive sections of drivers. Better balance of the ESD current flow is achieved by increasing the width and length of nulti-finger channels of semiconductor material defining the gates of the drivers in the active section. Wider, longer gates of the drivers in the active section increase their ability to carry current, thereby resulting in a more symmetrical distribution of ESD current between the active and inactive sections without degrading the IC's normal performance.

摘要翻译： 诸如输入 - 输出缓冲器的MOS集成电路通过平衡通过驱动器的有源和非有效部分的ESD电流来改善对静电放电（ESD）的损坏。 通过增加限定有源部分中的驱动器的栅极的半导体材料的多指通道的宽度和长度来实现ESD电流的更好的平衡。 有源部分的驱动器较长的栅极增加了其承载电流的能力，从而导致有源和非活动部分之间的ESD电流分布更为对称，而不会降低IC的正常性能。

公开(公告)号：US06703663B1

公开(公告)日：2004-03-09

申请号：US09655086

申请日：2000-09-05

申请人： Jian-Hsing Lee ,  Yi-Hsun Wu ,  Jian-Ren Shih

发明人： Jian-Hsing Lee ,  Yi-Hsun Wu ,  Jian-Ren Shih

IPC分类号： H01L2976

CPC分类号： H01L29/7833 ,  H01L21/823814 ,  H01L27/0266 ,  H01L29/1083

摘要： A method of forming a semiconductor memory device formed on a semiconductor substrate with an N-well and a P-well comprises the following steps. Form over a substrate the combination of a gate oxide layer and a gate layer patterned into gate stacks with sidewalls for an NMOS FET device over a P-well in the substrate and a PMOS FET device over an N-well. Form P− lightly doped S/D regions in the N-well and N− lightly doped S/D regions in the P-well. Form spacers on the sidewalls of the gate stacks. Thereafter form deep N− lightly doped S/D regions in the P-well, and form deep P− lightly doped S/D regions in the N-well. Form heavily doped P++ regions self-aligned with the gate below future P+ S/D sites to be formed self-aligned with the spacers in the N-well, and form heavily doped N++ regions self-aligned with the gate below future N+ S/D sites to be formed self-aligned with the spacers in the P-well.

摘要翻译： 用N阱和P阱形成在半导体衬底上的半导体存储器件的形成方法包括以下步骤。 在衬底上形成栅极氧化物层和栅极层的组合，栅极层与衬底中的P阱上的NMOS FET器件的侧壁和N阱上的PMOS FET器件构图成栅极堆叠。 在P阱中的N阱和N-轻掺杂的S / D区中形成P-轻掺杂的S / D区。 在栅极堆叠的侧壁上形成间隔物。 然后在P阱中形成深N轻掺杂的S / D区，并在N阱中形成深P-轻掺杂的S / D区。 形成与未来P + S / D位置下方的栅极自对准的重掺杂P ++区域，以与N阱中的间隔物自对准，并形成与未来N + S / D的栅极自对准的重掺杂N ++区域， D点与P阱中的间隔物自对准。

公开(公告)号：US06400542B1

公开(公告)日：2002-06-04

申请号：US09882680

申请日：2001-06-18

申请人： Jian-Hsing Lee ,  Jian-Ren Shih ,  Yi-Hsun Wu ,  Jing-Meng Liu

发明人： Jian-Hsing Lee ,  Jian-Ren Shih ,  Yi-Hsun Wu ,  Jing-Meng Liu

IPC分类号： H02H900

CPC分类号： H01L27/0259

摘要： A voltage clamping circuit that protects integrated circuits having multiple separate power supply voltage terminals from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage terminals. The voltage clamping circuit has two subgroups of Darlington connected clamping transistors. The first subgroup of Darlington connected clamping transistors is connected between the first power supply voltage terminal and the second power supply voltage terminal. If the differential voltage exceeds the first clamping voltage level, the first subgroup of Darlington connected clamping transistors turn on and restore the first differential voltage to a level less than the first clamping voltage level. The second subgroup of Darlington connected clamping transistors connected between the second power supply terminal and the first power supply terminal. If the differential voltage exceeds the second clamping voltage level, the second subgroup of Darlington connected transistors turn on and restore the differential voltage to a level less than the second clamping voltage level.

摘要翻译： 一种电压钳位电路，当ESD事件在多个分离的电源电压端子之间引起过大的差分电压时，保护具有多个单独的电源电压端子的集成电路免受损坏。 电压钳位电路有两个Darlington连接钳位晶体管的子组。 达林顿连接的钳位晶体管的第一个子组连接在第一电源电压端子和第二电源电压端子之间。 如果差分电压超过第一钳位电压电平，则达林顿连接的钳位晶体管的第一个子组导通，并将第一个差分电压恢复到小于第一钳位电压电平的电平。 连接在第二电源端子和第一电源端子之间的达林顿的第二子组连接钳位晶体管。 如果差分电压超过第二钳位电压电平，则达林顿连接晶体管的第二个子组导通，并将差分电压恢复到小于第二钳位电压电平的电平。

公开(公告)号：US20050275987A1

公开(公告)日：2005-12-15

申请号：US10867112

申请日：2004-06-14

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC分类号： H01L27/02 ,  H02H3/20 ,  H03K17/0814

CPC分类号： H03K17/08142 ,  H01L27/0266

摘要： An electrostatic discharge (ESD) protection circuit and method thereof are presented. In some embodiments, a high voltage tolerant input/output circuit comprises an ESD detection circuit, a first first-type transistor, a first second-type transistor, and a second second-type transistor. The first first-type transistor and the first second-type transistor are coupled to a pad. The ESD detection circuit determines whether ESD occurs at the pad and, if so, couples the gates of the first and second second-type transistors to the second power rail.

摘要翻译： 提出了一种静电放电（ESD）保护电路及其方法。 在一些实施例中，高耐压输入/输出电路包括ESD检测电路，第一第一型晶体管，第一第二型晶体管和第二第二型晶体管。 第一第一型晶体管和第一第二型晶体管耦合到焊盘。 ESD检测电路确定ESD是否发生在焊盘处，如果是，则将第一和第二第二型晶体管的栅极耦合到第二电源轨。

公开(公告)号：US07508639B2

公开(公告)日：2009-03-24

申请号：US11305983

申请日：2005-12-19

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC分类号： H02H9/00 ,  H02H3/22 ,  H02H1/00 ,  H02H1/04 ,  H02H9/06 ,  H01C7/12

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： Input/output devices with robustness of ESD protection are provided. An input/output device comprises an input/output pad, a first NMOS transistor, a second NMOS transistor and an ESD detector. The first NMOS transistor comprises a first drain, a first source and a first gate, wherein the first source and the first gate are coupled to a first ground power rail, and the first drain to the input/output pad. The second NMOS transistor comprises a second drain, a second source and a second gate, wherein the second source is coupled to the first ground power rail, the second drain to the input/output pad, and the second gate to a first pre-driver. When an ESD event is detected, the ESD detector makes the first pre-driver couple the second gate to the first ground power rail, thereby the first and second transistors evenly discharge ESD current.

摘要翻译： 提供具有ESD保护鲁棒性的输入/输出设备。 输入/输出装置包括输入/​​输出焊盘，第一NMOS晶体管，第二NMOS晶体管和ESD检测器。 第一NMOS晶体管包括第一漏极，第一源极和第一栅极，其中第一源极和第一栅极耦合到第一接地电源轨，第一漏极耦合到输入/输出焊盘。 第二NMOS晶体管包括第二漏极，第二源极和第二栅极，其中第二源极耦合到第一接地电源轨，第二漏极耦合到输入/输出焊盘，第二栅极耦合到第一预驱动器 。 当检测到ESD事件时，ESD检测器使第一预驱动器将第二栅极耦合到第一接地电源轨，由此第一和第二晶体管均匀地放电ESD电流。

公开(公告)号：US20060114629A1

公开(公告)日：2006-06-01

申请号：US11305983

申请日：2005-12-19

申请人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

发明人： Yi-Hsun Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC分类号： H02H9/00

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： Input/output devices with robustness of ESD protection are provided. An input/output device comprises an input/output pad, a first NMOS transistor, a second NMOS transistor and an ESD detector. The first NMOS transistor comprises a first drain, a first source and a first gate, wherein the first source and the first gate are coupled to a first ground power rail, and the first drain to the input/output pad. The second NMOS transistor comprises a second drain, a second source and a second gate, wherein the second source is coupled to the first ground power rail, the second drain to the input/output pad, and the second gate to a first pre-driver. When an ESD event is detected, the ESD detector makes the first pre-driver couple the second gate to the first ground power rail, thereby the first and second transistors evenly discharge ESD current.

公开(公告)号：US06323523B1

公开(公告)日：2001-11-27

申请号：US09494682

申请日：2000-01-31

申请人： Jian-Hsing Lee ,  Yi-Hsun Wu ,  Shui-Hung Chen ,  Jiaw-Ren Shih

发明人： Jian-Hsing Lee ,  Yi-Hsun Wu ,  Shui-Hung Chen ,  Jiaw-Ren Shih

IPC分类号： H01L2362

CPC分类号： H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protective circuit formed by n-type pull-up transistors and n-type pull-down transistors on a p-type silicon substrate for protecting an internal device circuit is disclosed. In the circuit, a n-well region having a p+ diffusion and a n+ diffusion therein being formed adjacent one drain region of one pull-up transistors, the p+ diffusion and a n+ diffusion, as well as all the drain regions of the pull-up transistors are coupled to a power supply. All the source regions of the pull-up transistors and drain regions of the pull-down transistors are connected to an I/O pad. All the source regions of the pull-down transistors including the p+ guardings are grounded. The gates of all transistors are connected to the internal device circuit so that the internal device circuit will be immunity from the ESD.

摘要翻译： 公开了一种用于保护内部器件电路的p型硅衬底上的n型上拉晶体管和n型下拉晶体管形成的ESD保护电路。 在该电路中，在一个上拉晶体管的一个漏极区附近形成有p +扩散和n +扩散的n阱区，p +扩散和n +扩散以及所述漏极区的所有漏极区， 上拉晶体管耦合到电源。 下拉晶体管的上拉晶体管和漏极区域的所有源极区域都连接到I / O焊盘。 包括p +保护的下拉晶体管的所有源极区域接地。 所有晶体管的栅极连接到内部器件电路，使得内部器件电路将免受ESD的影响。

公开(公告)号：US07462885B2

公开(公告)日：2008-12-09

申请号：US11606424

申请日：2006-11-30

申请人： Shui-Hung Chen ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  D. J. Perng ,  Anthony Oates

发明人： Shui-Hung Chen ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  D. J. Perng ,  Anthony Oates

IPC分类号： H01L29/72 ,  H01L23/62

CPC分类号： H01L29/0847 ,  H01L27/0266 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

摘要： An electrostatic discharge-protected MOS structure is disclosed. An electrostatic discharge-protected MOS structure includes a semiconductor substrate of a first type, a first well of the first type formed in the semiconductor substrate, and a second well of a second type disposed adjacent to the first well. The MOS structure further includes a source region, a drain region, and an oxide layer and a polysilicon layer for forming a gate electrode of the MOS structure. In addition, the MOS structure includes a parasitic SCR comprising at least a parasitic NPN bipolar transistor and a buried layer of the second type interposed between the second well and the semiconductor substrate. The buried layer functions to lower a resistance of the semiconductor substrate during an ESD event so that ESD currents generated by the parasitic SCR are dissipated through the buried layer and the semiconductor substrate, thereby protecting the MOS structure.

摘要翻译： 公开了一种静电放电保护的MOS结构。 静电放电保护的MOS结构包括第一类型的半导体衬底，形成在半导体衬底中的第一类型的第一阱和与第一阱相邻布置的第二类型的第二阱。 MOS结构还包括用于形成MOS结构的栅电极的源极区，漏极区和氧化物层以及多晶硅层。 此外，MOS结构包括至少包括寄生NPN双极晶体管和插入在第二阱和半导体衬底之间的第二类型的掩埋层的寄生SCR。 掩埋层用于在ESD事件期间降低半导体衬底的电阻，使得由寄生SCR产生的ESD电流通过掩埋层和半导体衬底消散，从而保护MOS结构。

公开(公告)号：US06306695B1

公开(公告)日：2001-10-23

申请号：US09407110

申请日：1999-09-27

申请人： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-Hung Chen ,  Yi-Hsun Wu

发明人： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-Hung Chen ,  Yi-Hsun Wu

IPC分类号： H01L2100

CPC分类号： H01L27/0277 ,  H01L27/0259 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors. When contacting an ESD voltage source to the collectors of the plurality of parasitic bipolar junction transistors, the junction formed between the collector and the base of the parasitic bipolar junction transistor enters into avalanche breakdown. The avalanche breakdown generates a large current through the substrate bulk resistances that is sufficiently large as to cause the base emitter junctions of all the parasitic bipolar junction transistors and turn on the parasitic bipolar junction transistors. The conduction of all the parasitic bipolar junction transistors is sufficient to cause the ESD voltage to be discharged thus preventing damage to the internal circuitry.

摘要翻译： 在半导体衬底上形成防止集成电路的内部电路的ESD保护电路，以防止在来自ESD电压源的极端电压电平期间的损坏并连接到输入/输出焊盘。 多个MOS FET的漏极形成在半导体衬底的表面内，并且各自连接到输入/输出焊盘。 多个MOS FET的多个源极形成在半导体衬底的表面内并且被放置在与多个漏极相距一定距离处并连接到接地参考电位。 多个源的对彼此相邻。 放置在源对之间的每个源之间并被允许浮动的多个隔离区域。 多个MOS FET具有多个寄生双极结型晶体管。 当将ESD电压源接触到多个寄生双极结型晶体管的集电极时，在集电极与寄生双极结型晶体管的基极之间形成的结形成为雪崩击穿。 雪崩击穿通过衬底体电阻产生大的电流，该电阻足够大，以致引起所有寄生双极结型晶体管的基极发射极结并导通寄生双极结型晶体管。 所有寄生双极结晶体管的导通足以使ESD电压放电，从而防止对内部电路的损坏。

公开(公告)号：US20080128818A1

公开(公告)日：2008-06-05

申请号：US11606424

申请日：2006-11-30

申请人： Shui-Hung Chen ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  D. J. Perng ,  Anthony Oates

发明人： Shui-Hung Chen ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  D. J. Perng ,  Anthony Oates

IPC分类号： H01L27/06

CPC分类号： H01L29/0847 ,  H01L27/0266 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

摘要： An electrostatic discharge-protected MOS structure is disclosed. An electrostatic discharge-protected MOS structure includes a semiconductor substrate of a first type, a first well of the first type formed in the semiconductor substrate, and a second well of a second type disposed adjacent to the first well. The MOS structure further includes a source region, a drain region, and an oxide layer and a polysilicon layer for forming a gate electrode of the MOS structure. In addition, the MOS structure includes a parasitic SCR comprising at least a parasitic NPN bipolar transistor and a buried layer of the second type interposed between the second well and the semiconductor substrate. The buried layer functions to lower a resistance of the semiconductor substrate during an ESD event so that ESD currents generated by the parasitic SCR are dissipated through the buried layer and the semiconductor substrate, thereby protecting the MOS structure.