公开(公告)号：US07385244B2

公开(公告)日：2008-06-10

申请号：US11051845

申请日：2005-02-03

申请人： Yi-Shing Chang ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Wen-Ting Chu

发明人： Yi-Shing Chang ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Wen-Ting Chu

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

摘要： A method for forming an improved etching hardmask oxide layer in a polysilicon etching process including providing a planarized semiconductor wafer process surface including adjacent first exposed polysilicon portions and exposed oxide portions; selectively etching through a thickness portion of the exposed oxide portions; thermally growing an oxide hardmask layer over the exposed polysilicon portions to form oxide hardmask portions; exposing second exposed polysilicon portions adjacent at least one oxide hardmask portion; and, etching through a thickness portion of the second exposed polysilicon portions.

摘要翻译： 一种在多晶硅蚀刻工艺中形成改进的蚀刻硬掩模氧化物层的方法，包括提供包括相邻的第一裸露多晶硅部分和暴露的氧化物部分的平坦化的半导体晶片工艺表面; 选择性地蚀刻暴露的氧化物部分的厚度部分; 在暴露的多晶硅部分上热生长氧化物硬掩模层以形成氧化物硬掩模部分; 暴露出与至少一个氧化物硬掩模部分相邻的第二暴露的多晶硅部分; 并且蚀刻穿过第二暴露的多晶硅部分的厚度部分。

公开(公告)号：US07030444B2

公开(公告)日：2006-04-18

申请号：US10786798

申请日：2004-02-25

申请人： Kuo-Chi Tu ,  Wen-Ting Chu ,  Yi-Shing Chang ,  Yi-Jiun Lin

发明人： Kuo-Chi Tu ,  Wen-Ting Chu ,  Yi-Shing Chang ,  Yi-Jiun Lin

IPC分类号： H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A split gate flash memory cell structure is disclosed for prevention of reverse tunneling. A gate insulator layer is formed over a semiconductor surface and a floating gate is disposed over the gate insulator layer. A floating gate insulator layer is disposed over the floating gate and sidewall insulator spacers are disposed along bottom portions of the floating gate sidewall adjacent to said gate insulator layer. The sidewall insulator spacers are formed from a spacer insulator layer that had been deposited in a manner that constitutes a minimal expenditure of an available thermal budget and etching processes used in fashioning the sidewall insulator spacers etch the spacer insulator layer faster than the gate insulator layer and the floating gate insulator layer. An intergate insulator layer is disposed over exposed portions of the gate insulator layer, the floating gate, the floating gate insulator layer and the sidewall insulator spacers. A conductive control gate is disposed over the intergate insulator layer, covering about half of the floating gate.

摘要翻译： 公开了一种用于防止反向隧道的分裂门闪存单元结构。 在半导体表面上形成栅极绝缘体层，并且在栅极绝缘体层上方设置浮置栅极。 浮置栅极绝缘体层设置在浮置栅极之上，并且侧壁绝缘体间隔物沿邻近所述栅极绝缘体层的浮动栅极侧壁的底部设置。 侧壁绝缘体间隔物由间隔绝缘体层形成，该间隔绝缘体层以构成可用热预算的最小消耗量的方式沉积，并且蚀刻工艺用于形成侧壁绝缘体间隔层比栅极绝缘体层更快蚀刻间隔绝缘体层， 浮栅绝缘体层。 栅极绝缘体层设置在栅极绝缘体层，浮置栅极，浮置栅极绝缘体层和侧壁绝缘体间隔物的暴露部分之上。 导电控制栅极设置在栅极绝缘体层之上，覆盖浮动栅极的大约一半。

公开(公告)号：US07227218B2

公开(公告)日：2007-06-05

申请号：US11094035

申请日：2005-03-30

申请人： Yi-Shing Chang ,  Wen-Ting Chu

发明人： Yi-Shing Chang ,  Wen-Ting Chu

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A memory device and the method for manufacturing same is disclosed. The device comprises a first oxide layer on top of a substrate, a floating gate layer on top of the first oxide layer, a second oxide layer over the floating gate layer, wherein the second oxide layer and the floating gate layer have a first opening and a second opening respectively, and wherein the width of second opening is bigger than the width of the narrowest region of the first opening so that the floating gate layer is pulled back horizontally underneath the second oxide layer. A source region is in the substrate underneath the first oxide layer, and a third oxide layer fills in the first and second openings conforming to the contour thereof, wherein the third oxide has a third opening to reach a portion of the source region. Further, a control gate material fills in the third opening.

摘要翻译： 公开了一种存储器件及其制造方法。 该器件包括在衬底的顶部上的第一氧化物层，在第一氧化物层的顶部上的浮动栅极层，浮置栅极层上的第二氧化物层，其中第二氧化物层和浮动栅极层具有第一开口和 第二开口，其中第二开口的宽度大于第一开口的最窄区域的宽度，使得浮栅层在第二氧化物层下方被水平地拉回。 源区域位于第一氧化物层下方的衬底中，并且第三氧化物层填充符合其轮廓的第一和第二开口，其中第三氧化物具有到达源极区域的一部分的第三开口。 此外，控制门材料填充在第三开口中。

公开(公告)号：US06890821B2

公开(公告)日：2005-05-10

申请号：US10617470

申请日：2003-07-11

申请人： Yi-Shing Chang ,  Wen-Ting Chu

发明人： Yi-Shing Chang ,  Wen-Ting Chu

IPC分类号： H01L21/336 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A memory device and the method for manufacturing the same is disclosed. The device includes a first oxide layer on top of a substrate, a floating gate layer on top of the first oxide layer, and a second oxide layer over the floating gate layer. The second oxide layer and the floating gate layer have a first opening and a second opening respectively wherein the width of second opening is bigger than the width of the narrowest region of the first opening so that the floating gate layer is pulled back horizontally underneath the second oxide layer. A source region is in the substrate underneath the first oxide layer, and a third oxide layer fills in the first and second openings conforming to the contour thereof. The third oxide has a third opening to reach a portion of the source region. Further, a control gate material fills in the third opening.

公开(公告)号：US20050179080A1

公开(公告)日：2005-08-18

申请号：US11094035

申请日：2005-03-30

申请人： Yi-Shing Chang ,  Wen-Ting Chu

发明人： Yi-Shing Chang ,  Wen-Ting Chu

IPC分类号： H01L21/336 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A memory device and the method for manufacturing same is disclosed. The device comprises a first oxide layer on top of a substrate, a floating gate layer on top of the first oxide layer, a second oxide layer over the floating gate layer, wherein the second oxide layer and the floating gate layer have a first opening and a second opening respectively, and wherein the width of second opening is bigger than the width of the narrowest region of the first opening so that the floating gate layer is pulled back horizontally underneath the second oxide layer. A source region is in the substrate underneath the first oxide layer, and a third oxide layer fills in the first and second openings conforming to the contour thereof, wherein the third oxide has a third opening to reach a portion of the source region. Further, a control gate material fills in the third opening.

摘要翻译： 公开了一种存储器件及其制造方法。 该器件包括在衬底的顶部上的第一氧化物层，在第一氧化物层的顶部上的浮动栅极层，浮置栅极层上的第二氧化物层，其中第二氧化物层和浮动栅极层具有第一开口和 第二开口，其中第二开口的宽度大于第一开口的最窄区域的宽度，使得浮栅层在第二氧化物层下方被水平地拉回。 源区域位于第一氧化物层下方的衬底中，并且第三氧化物层填充符合其轮廓的第一和第二开口，其中第三氧化物具有到达源极区域的一部分的第三开口。 此外，控制门材料填充在第三开口中。

公开(公告)号：US20050009273A1

公开(公告)日：2005-01-13

申请号：US10617470

申请日：2003-07-11

申请人： Yi-Shing Chang ,  Wen-Ting Chu

发明人： Yi-Shing Chang ,  Wen-Ting Chu

IPC分类号： H01L21/336 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A memory device and the method for manufacturing the same is disclosed. The device includes a first oxide layer on top of a substrate, a floating gate layer on top of the first oxide layer, and a second oxide layer over the floating gate layer. The second oxide layer and the floating gate layer have a first opening and a second opening respectively wherein the width of second opening is bigger than the width of the narrowest region of the first opening so that the floating gate layer is pulled back horizontally underneath the second oxide layer. A source region is in the substrate underneath the first oxide layer, and a third oxide layer fills in the first and second openings conforming to the contour thereof. The third oxide has a third opening to reach a portion of the source region. Further, a control gate material fills in the third opening.

摘要翻译： 公开了一种存储器件及其制造方法。 该器件包括在衬底的顶部上的第一氧化物层，在第一氧化物层的顶部上的浮动栅极层和浮置栅极层上的第二氧化物层。 第二氧化物层和浮栅层分别具有第一开口和第二开口，其中第二开口的宽度大于第一开口的最窄区域的宽度，使得浮栅层在第二开口和第二开口的第二开口下方水平地被拉回 氧化层。 源区域位于第一氧化物层下方的衬底中，并且第三氧化物层填充符合其轮廓的第一和第二开口。 第三氧化物具有第三开口以到达源区的一部分。 此外，控制门材料填充在第三开口中。

公开(公告)号：US20050184331A1

公开(公告)日：2005-08-25

申请号：US10786798

申请日：2004-02-25

申请人： Kuo-Chi Tu ,  Wen-Ting Chu ,  Yi-Shing Chang ,  Yi-Jiun Lin

发明人： Kuo-Chi Tu ,  Wen-Ting Chu ,  Yi-Shing Chang ,  Yi-Jiun Lin

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A split gate flash memory cell structure is disclosed for prevention of reverse tunneling. A gate insulator layer is formed over a semiconductor surface and a floating gate is disposed over the gate insulator layer. A floating gate insulator layer is disposed over the floating gate and sidewall insulator spacers are disposed along bottom portions of the floating gate sidewall adjacent to said gate insulator layer. The sidewall insulator spacers are formed from a spacer insulator layer that had been deposited in a manner that constitutes a minimal expenditure of an available thermal budget and etching processes used in fashioning the sidewall insulator spacers etch the spacer insulator layer faster than the gate insulator layer and the floating gate insulator layer. An intergate insulator layer is disposed over exposed portions of the gate insulator layer, the floating gate, the floating gate insulator layer and the sidewall insulator spacers. A conductive control gate is disposed over the intergate insulator layer, covering about half of the floating gate.

摘要翻译： 公开了一种用于防止反向隧道的分裂门闪存单元结构。 在半导体表面上形成栅极绝缘体层，并且在栅极绝缘体层上方设置浮置栅极。 浮置栅极绝缘体层设置在浮置栅极之上，并且侧壁绝缘体间隔物沿邻近所述栅极绝缘体层的浮动栅极侧壁的底部设置。 侧壁绝缘体间隔物由间隔绝缘体层形成，该间隔绝缘体层以构成可用热预算的最小消耗量的方式沉积，并且蚀刻工艺用于形成侧壁绝缘体间隔层比栅极绝缘体层更快蚀刻间隔绝缘体层， 浮栅绝缘体层。 栅极绝缘体层设置在栅极绝缘体层，浮置栅极，浮置栅极绝缘体层和侧壁绝缘体间隔物的暴露部分之上。 导电控制栅极设置在栅极绝缘体层之上，覆盖浮动栅极的大约一半。

公开(公告)号：US20050133850A1

公开(公告)日：2005-06-23

申请号：US11051845

申请日：2005-02-03

申请人： Yi-Shing Chang ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Wen-Ting Chu

发明人： Yi-Shing Chang ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Wen-Ting Chu

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/76 ,  H01L21/3205 ,  H01L21/461

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

摘要： A method for forming an improved etching hardmask oxide layer in a polysilicon etching process including providing a planarized semiconductor wafer process surface including adjacent first exposed polysilicon portions and exposed oxide portions; selectively etching through a thickness portion of the exposed oxide portions; thermally growing an oxide hardmask layer over the exposed polysilicon portions to form oxide hardmask portions; exposing second exposed polysilicon portions adjacent at least one oxide hardmask portion; and, etching through a thickness portion of the second exposed polysilicon portions.

公开(公告)号：US06855602B2

公开(公告)日：2005-02-15

申请号：US10401941

申请日：2003-03-27

申请人： Yi-Shing Chang ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Wen-Ting Chu

发明人： Yi-Shing Chang ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Wen-Ting Chu

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/62

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

摘要： A method for forming an improved etching hardmask oxide layer in a polysilicon etching process including providing a planarized semiconductor wafer process surface including adjacent first exposed polysilicon portions and exposed oxide portions; selectively etching through a thickness portion of the exposed oxide portions; thermally growing an oxide hardmask layer over the exposed polysilicon portions to form oxide hardmask portions; exposing second exposed polysilicon portions adjacent at least one oxide hardmask portion; and, etching through a thickness portion of the second exposed polysilicon portions.

摘要翻译： 一种在多晶硅蚀刻工艺中形成改进的蚀刻硬掩模氧化物层的方法，包括提供包括相邻的第一裸露多晶硅部分和暴露的氧化物部分的平坦化的半导体晶片工艺表面; 选择性地蚀刻暴露的氧化物部分的厚度部分; 在暴露的多晶硅部分上热生长氧化物硬掩模层以形成氧化物硬掩模部分; 暴露出与至少一个氧化物硬掩模部分相邻的第二暴露的多晶硅部分; 并且蚀刻穿过第二暴露的多晶硅部分的厚度部分。

公开(公告)号：US20140021584A1

公开(公告)日：2014-01-23

申请号：US13553086

申请日：2012-07-19

申请人： Kuo-Chi Tu ,  Wen-Ting Chu

发明人： Kuo-Chi Tu ,  Wen-Ting Chu

IPC分类号： H01L29/86 ,  H01L21/02

CPC分类号： H01L23/5223 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/2436 ,  H01L28/40 ,  H01L29/94 ,  H01L45/04 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is decoupling capacitor device. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor.

摘要翻译： 提供去耦电容器件。 去耦电容器装置包括在沉积工艺中沉积的第一电介质层部分，其沉积用于非易失性存储单元的第二电介质层部分。 使用单个掩模对两个部分进行图案化。 还提供了片上系统（SOC）器件，SOC包括位于单个金属间介电层中的RRAM单元和去耦电容器。 还提供了一种形成工艺兼容去耦电容器的方法。 该方法包括图案化顶部电极层，绝缘层和底部电极层，以形成非易失性存储元件和去耦电容器。