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1.发明授权Double mill process for patterning current perpendicular to plane (CPP) magnetoresistive devices to minimize barrier shorting and barrier damage 失效用于图形化垂直于平面（CPP）磁阻器件的电流的双轧机工艺，以最小化障碍物短路和屏障损坏公开(公告)号：US07639456B2
公开(公告)日：2009-12-29
申请号：US11246720
申请日：2005-10-06
IPC分类号： G11B5/39
CPC分类号： G11B5/398 , B82Y25/00 , G01R33/093 , G11B5/3163 , G11B5/3906
摘要： A current perpendicular to plane (CPP) sensor and method of manufacturing such a sensor that prevents current shunting at the sides of the barrier/spacer layer due to redeposited material. A first ion mill is performed to remove at least the free layer. A quick glancing ion mill can be performed to remove the small amount of redep that may have accumulated on the sides of the free layer and barrier/spacer layer. Then an insulation layer is deposited to protect the sides of the free layer/barrier layer during subsequent manufacturing which can include further ion milling to define the rest of the sensor and another glancing ion mill to remove the redep formed by the further ion milling. This results in a sensor having no current shunting at the sides of the sensor and having no damage to the sensor layers.
摘要翻译： 垂直于平面（CPP）传感器的电流和制造这种传感器的方法，其防止由于再沉积材料在阻挡层/间隔层的侧面的电流分流。 执行第一离子研磨以去除至少自由层。 可以进行快速扫查离子磨，以除去可能积聚在自由层和阻挡层/间隔层的侧面上的少量重排物。 然后沉积绝缘层以在随后的制造期间保护自由层/阻挡层的侧面，其可以包括进一步的离子铣削以限定传感器的其余部分和另一个扫掠离子磨机以移除由进一步的离子铣削形成的重复。 这导致传感器在传感器的侧面没有电流分流并且不会损坏传感器层。
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公开(公告)号：US08037593B2
公开(公告)日：2011-10-18
申请号：US11966106
申请日：2007-12-28
CPC分类号： G11B5/3163 , B82Y25/00 , G01R33/093 , G11B5/398 , Y10T29/49021 , Y10T29/49032 , Y10T29/49039 , Y10T29/49043 , Y10T29/49044
摘要： A method for manufacturing a magnetoresistive sensor that decreases the stack height of the sensor. The method includes forming a sensor structure having at its top, a Ru layer and a Ta layer over the Ru layer. An annealing process is performed to set the magnetization of the pinned layer of the sensor structure. After the annealing process has been completed and the Ta layer is no longer needed, an ion milling process is performed to remove the Ta layer.
摘要翻译： 一种降低传感器堆叠高度的磁阻传感器的制造方法。 该方法包括形成传感器结构，其顶部具有在Ru层上的Ru层和Ta层。 执行退火处理以设置传感器结构的钉扎层的磁化。 在完成退火处理并且不再需要Ta层之后，执行离子铣削处理以去除Ta层。
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3.发明授权公开(公告)号：US07839607B2
公开(公告)日：2010-11-23
申请号：US11890868
申请日：2007-08-07
IPC分类号： G11B5/127
CPC分类号： B82Y10/00 , B82Y25/00 , G11B5/3163 , G11B5/3932 , G11B2005/3996 , Y10T428/1171
摘要： A method is presented for fabricating a CPP read head having a CPP read head sensor and a hard bias layer which includes forming a strip of sensor material in a sensor material region, and depositing strips of fast-milling dielectric material in first and second fast-milling dielectric material regions adjacent to the sensor material region. A protective layer and a layer of masking material are deposited on the strip of sensor material and the strips of fast-milling dielectric material to provide masked areas and exposed areas. A shaping source, such as an ion milling source, is provided which shapes the exposed areas. Hard bias material is then deposited on the regions of sensor material and fast-milling dielectric material to form caps on each of these regions. The caps of hard bias material and the masking material are then removed from each of these regions.
摘要翻译： 提出了一种用于制造具有CPP读取头传感器和硬偏置层的CPP读取头的方法，该CPP读取头包括在传感器材料区域中形成传感器材料条，以及将快速研磨电介质材料的条带放置在第一和第二快速接头中， 研磨与传感器材料区域相邻的介电材料区域。 保护层和掩蔽材料层沉积在传感器材料条和快速研磨电介质材料条上，以提供掩蔽区域和暴露区域。 提供成形源，例如离子铣削源，其形成暴露的区域。 然后将硬偏置材料沉积在传感器材料和快速研磨电介质材料的区域上，以在这些区域中的每一个上形成盖。 然后从这些区域中的每一个去除硬偏置材料的盖子和掩模材料。
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4.发明授权Method of partial depth material removal for fabrication of CPP read sensor 失效用于制造CPP读取传感器的部分深度材料去除方法公开(公告)号：US07419610B2
公开(公告)日：2008-09-02
申请号：US11197957
申请日：2005-08-05
IPC分类号： B44C1/22
CPC分类号： H01F41/308 , B82Y25/00 , B82Y40/00 , G11B5/3163 , G11B5/3903 , H01F10/3268 , Y10T29/49032 , Y10T29/49044
摘要： A method for fabricating a read head sensor for a magnetic disk drive is presented. The method includes providing a layered wafer stack to be shaped, where the layered wafer stack includes a free layer, a barrier layer and a pinned layer. A single- or multi-layered photoresist mask is formed upon the layered wafer stack to be shaped. A material removal source is provided and used to perform a partial depth material removal within a partial depth material removal range which extends from the free layer to within the pinned layer to a partial depth material removal endpoint. In various embodiments, this depth endpoint lies at or within the barrier layer or within but not through the pinned layer.
摘要翻译： 提出了一种用于制造用于磁盘驱动器的读取头传感器的方法。 该方法包括提供待成形的层状晶片叠层，其中层状晶片堆叠包括自由层，阻挡层和钉扎层。 单层或多层光刻胶掩模形成在待成形的层状晶片叠层上。 提供材料去除源并用于在部分深度材料去除范围内执行部分深度材料去除，该部分深度材料去除范围从自由层延伸到钉扎层内至部分深度材料去除端点。 在各种实施例中，该深度端点位于或在阻挡层内或内部但不穿过被钉扎层。
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公开(公告)号：US20090165286A1
公开(公告)日：2009-07-02
申请号：US11966106
申请日：2007-12-28
IPC分类号： G11B5/127
CPC分类号： G11B5/3163 , B82Y25/00 , G01R33/093 , G11B5/398 , Y10T29/49021 , Y10T29/49032 , Y10T29/49039 , Y10T29/49043 , Y10T29/49044
摘要： A method for manufacturing a magnetoresistive sensor that decreases the stack height of the sensor. The method includes forming a sensor structure having at its top, a Ru layer and a Ta layer over the Ru layer. An annealing process is performed to set the magnetization of the pinned layer of the sensor structure. After the annealing process has been completed and the Ta layer is no longer needed, an ion milling process is performed to remove the Ta layer.
摘要翻译： 一种降低传感器堆叠高度的磁阻传感器的制造方法。 该方法包括形成传感器结构，其顶部具有在Ru层上的Ru层和Ta层。 执行退火处理以设置传感器结构的钉扎层的磁化。 在完成退火处理并且不再需要Ta层之后，执行离子铣削处理以去除Ta层。
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6.发明授权Dual angle milling for current perpendicular to plane (CPP) magnetoresistive sensor definition 失效用于垂直于平面（CPP）磁阻传感器定义的电流的双角铣削公开(公告)号：US07329362B2
公开(公告)日：2008-02-12
申请号：US11200757
申请日：2005-08-09
IPC分类号： B44C1/22
CPC分类号： B82Y10/00 , B82Y25/00 , G01R33/09 , G11B5/3163 , G11B5/3903 , G11B5/3909 , G11B2005/3996 , H01J2237/3114 , H01L43/08 , H01L43/12 , Y10T29/49046
摘要： A method for constructing a magnetoresistive sensor which eliminates all redeposited material (redep) from the sides of the sensor. The method involves forming a mask over a plurality of sensor layers, and then performing an ion mill at an angle that is nearly normal to the surface of the sensor layers. A second (glancing) ion mill is then performed at a larger angle with respect to the normal. The first ion mill may be 0-30 degrees with respect to normal, whereas the second ion mill can be 50-89 degrees with respect to normal. The first ion mill is performed with a larger bias voltage than the second ion mill. The higher bias voltage of the first ion mill provides a well collimated ion beam to form straight vertical side walls. The lower bias voltage of the second ion mill prevent damage to the sensor layers during the removal of redep from the sides of the sensor.
摘要翻译： 一种用于构造磁阻传感器的方法，其从传感器的侧面消除所有再沉积的材料（重新进行）。 该方法包括在多个传感器层上形成掩模，然后以与传感器层的表面几乎垂直的角度执行离子磨。 然后相对于法线以较大的角度执行第二（扫视）离子磨。 第一离子磨可相对于正常为0-30度，而第二离子磨可相对于正常为50-89度。 第一离子磨机以比第二离子磨机更大的偏压进行。 第一离子磨的较高的偏置电压提供了准直的离子束以形成直立的垂直侧壁。 第二离子磨的偏置电压较低可以防止传感器层从传感器的侧面移除重新进行检测。
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公开(公告)号：USD1004072S1
公开(公告)日：2023-11-07
申请号：US29823920
申请日：2022-01-20
申请人： Ying Hong
设计人： Ying Hong
摘要： FIG. 1 is a front, right side, top perspective view of a breast milk collector showing my new design;
FIG. 2 is a rear, right side, bottom perspective view thereof;
FIG. 3 is a front elevational view thereof;
FIG. 4 is a rear elevational view thereof;
FIG. 5 is a left side elevational view thereof;
FIG. 6 is a right side elevational view thereof;
FIG. 7 is a top plan view thereof; and,
FIG. 8 is a bottom plan view thereof.
The broken lines in the drawings depict portions of the breast milk collector that form no part of the claimed design.-
公开(公告)号：US11699588B2
公开(公告)日：2023-07-11
申请号：US17695336
申请日：2022-03-15
申请人： Ying Hong
发明人： Ying Hong
IPC分类号： H01L21/02 , H01L27/12 , H01L29/04 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/786
CPC分类号： H01L21/02672 , H01L21/02502 , H01L27/1222 , H01L27/1277 , H01L29/045 , H01L29/0673 , H01L29/42392 , H01L29/66757 , H01L29/66772 , H01L29/78642 , H01L21/02488 , H01L21/02491 , H01L21/02532 , H01L21/02595 , H01L29/0676
摘要： A vertical nanowire semiconductor device manufactured by a method of manufacturing a vertical nanowire semiconductor device is provided. The vertical nanowire semiconductor device includes a substrate, a first conductive layer in a source or drain area formed above the substrate, a semiconductor nanowire of a channel area vertically upright with respect to the substrate on the first conductive layer, wherein a crystal structure thereof is grown in orientation, a second conductive layer of a drain or source area provided on the top of the semiconductor nanowire, a metal layer on the second conductive layer, a NiSi2 contact layer between the second conductive layer and the metal layer, a gate surrounding the channel area of the vertical nanowire, and a gate insulating layer located between the channel area and the gate.
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公开(公告)号：US11631752B2
公开(公告)日：2023-04-18
申请号：US17584903
申请日：2022-01-26
申请人： Ying Hong
发明人： Ying Hong
摘要： A semiconductor device include a substrate, a buffer layer formed on the substrate, a channel layer formed by an intrinsic polycrystalline silicon layer on the buffer layer, polycrystalline source and drain by non-intrinsic silicon formed on both sides of the polycrystalline silicon layer, a source electrode and a drain electrode formed on the polycrystalline source and the drain, a gate electrode corresponding to the channel layer, and an NiSi2 contact layer located between the source and the source electrode and between the drain and the drain electrode.
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公开(公告)号：US11342448B2
公开(公告)日：2022-05-24
申请号：US17028337
申请日：2020-09-22
申请人： Ying Hong
发明人： Ying Hong
摘要： Provided is a method of manufacturing a semiconductor device, the method including: forming an insulating layer on a substrate; forming a trench, which extends in a first direction parallel with the plane of the substrate, to a preset depth in the insulating layer in a second direction perpendicular to the plane of the substrate; forming a plurality of amorphous silicon strips, which extend from the inside of the trench in the second direction intersecting with the first direction, in parallel in a first direction; forming a spacer on a side of the amorphous silicon strip by using an insulating material layer; and crystallizing the amorphous silicon strip by heat treatment, wherein crystal nucleation sites are formed in the amorphous silicon layer in the trench, and a polycrystalline silicon layer is formed by lateral grain growth in a longitudinal direction of the amorphous silicon strip from the crystal nucleation site.
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