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    Stacked semiconductor device
    1.
    发明授权
    Stacked semiconductor device 有权
    堆叠半导体器件

    公开(公告)号：US07768867B2

    公开(公告)日：2010-08-03

    申请号：US11761470

    申请日：2007-06-12

    申请人： Yoji Nishio ,  Yutaka Uematsu ,  Seiji Funaba ,  Hideki Osaka ,  Tsutomu Hara ,  Koichiro Aoki

    发明人： Yoji Nishio ,  Yutaka Uematsu ,  Seiji Funaba ,  Hideki Osaka ,  Tsutomu Hara ,  Koichiro Aoki

    IPC分类号： G11C8/00

    CPC分类号： G11C7/02 ,  G11C5/02 ,  G11C5/04 ,  H01L25/105 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

    摘要： Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.

    摘要翻译： 叠层半导体器件包括多个存储器芯片，堆叠在一起，其中高速传输中的波形失真被去除。 堆叠半导体器件1包括堆叠在一起的多个存储器芯片11,12。 作为用于每周期两次输入/输出数据的控制信号的数据选通信号（DQS）和反相数据选通信号（/ DQS）被用作两个单端数据选通信号。 数据选通信号和反相数据选通信号相互配合。 用于数据选通信号L4的数据选通信号线连接到第一存储芯片11的数据选通信号（DQS）焊盘。用于/ DQS信号L5的反相数据选通信号线连接到第二存储芯片11的反相数据选通信号（/ DQS）焊盘 存储芯片12。

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20080054379A1

    公开(公告)日：2008-03-06

    申请号：US11675476

    申请日：2007-02-15

    申请人： Yoji Nishio ,  Yutaka Uematsu ,  Hideki Osaka ,  Tsutomu Hara ,  Seiji Funaba

    发明人： Yoji Nishio ,  Yutaka Uematsu ,  Hideki Osaka ,  Tsutomu Hara ,  Seiji Funaba

    IPC分类号： H01L29/94

    CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C7/109

    摘要： Input circuit ensuring a noise margin for a reference voltage. A semiconductor chip 11a comprises a pad 14 that inputs a reference voltage Vref, an input circuit 13, a resistance element R1 connected between an input terminal of the input circuit 13 and the pad 14, a capacitance element C1 connected between the input terminal of the input circuit 13 and a power supply VDD, and a capacitance element C2 connected between the input terminal of the input circuit 13 and a ground VSS within the semiconductor chip. A resistance value of the resistance element R1 is set based on an impedance characteristic of a network, for supplying the reference voltage Vref.

    摘要翻译： 输入电路确保参考电压的噪声容限。 半导体芯片11a包括输入参考电压Vref的焊盘14，连接在输入电路13的输入端子和焊盘14之间的电阻元件R 1，连接在输入端13之间的电容元件C 1 输入电路13的端子和电源VDD，以及连接在输入电路13的输入端子和半导体芯片内的接地VSS之间的电容元件C 2。 基于网络的阻抗特性来设定电阻元件R 1的电阻值，用于提供基准电压Vref。

    Semiconductor memory device having input first-stage circuit
    7.
    发明授权
    Semiconductor memory device having input first-stage circuit 有权
    具有输入第一级电路的半导体存储器件

    公开(公告)号：US07889584B2

    公开(公告)日：2011-02-15

    申请号：US11580275

    申请日：2006-10-13

    申请人： Yoji Idei ,  Susumu Hatano ,  Yoji Nishio ,  Seiji Funaba ,  Yutaka Uematsu

    发明人： Yoji Idei ,  Susumu Hatano ,  Yoji Nishio ,  Seiji Funaba ,  Yutaka Uematsu

    IPC分类号： G11C7/02

    CPC分类号： G11C11/4074 ,  G11C5/147

    摘要： A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.

    摘要翻译： 本发明的半导体存储器件基于预定的参考电压确定信号的逻辑电平。 并且存储器件具有输入具有参考电压的参考信号的输入端子，连接到输入端子的低通滤波器，用于通过参考信号的参考电压的分量并消除不期望的高频分量，以及 一个或多个输入第一级电路分别连接低通滤波器的输出和具有待确定逻辑电平的信号。 在存储器件中，低通滤波器至少在工作时钟的频率上具有预定的衰减。

    Semiconductor memory device and memory module
    8.
    发明申请
    Semiconductor memory device and memory module 有权
    半导体存储器件和存储器模块

    公开(公告)号：US20070085601A1

    公开(公告)日：2007-04-19

    申请号：US11580275

    申请日：2006-10-13

    申请人： Yoji Idei ,  Susumu Hatano ,  Yoji Nishio ,  Seiji Funaba ,  Yutaka Uematsu

    发明人： Yoji Idei ,  Susumu Hatano ,  Yoji Nishio ,  Seiji Funaba ,  Yutaka Uematsu

    IPC分类号： H03B1/00

    CPC分类号： G11C11/4074 ,  G11C5/147

    摘要： A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.

    摘要翻译： 本发明的半导体存储器件基于预定的参考电压确定信号的逻辑电平。 并且存储器件具有输入具有参考电压的参考信号的输入端子，连接到输入端子的低通滤波器，用于通过参考信号的参考电压的分量并消除不期望的高频分量，以及 一个或多个输入第一级电路分别连接低通滤波器的输出和具有待确定逻辑电平的信号。 在存储器件中，低通滤波器至少在工作时钟的频率上具有预定的衰减。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US07319267B2

    公开(公告)日：2008-01-15

    申请号：US11712440

    申请日：2007-03-01

    申请人： Yutaka Uematsu ,  Hideki Osaka ,  Yoji Nishio ,  Yukitoshi Hirose

    发明人： Yutaka Uematsu ,  Hideki Osaka ,  Yoji Nishio ,  Yukitoshi Hirose

    IPC分类号： H01L23/02 ,  H01L23/34

    CPC分类号： H01L23/642 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/5286 ,  H01L23/647 ,  H01L25/105 ,  H01L2224/73204 ,  H01L2924/19105 ,  H01L2924/3011

    摘要： In a prior art, there has been a method in which a power supply line of an output buffer and that of a control circuit are independently provided so that the power supply noise occurring in the control circuit will not affect the output buffer. However, this method has had the problems that it increases both the number of power supply/grounding pins and power feed line inductance.The present invention provides a technique which, without causing the above two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.

    摘要翻译： 在现有技术中，存在一种方法，其中独立地提供输出缓冲器的电源线和控制电路的电源线，使得控制电路中出现的电源噪声不会影响输出缓冲器。 然而，该方法存在增加电源/接地引脚数和馈电线电感的问题。 本发明提供一种技术，其不会引起上述两个问题，即（1）增加电源/接地引脚数量和（2）增加的馈电线电感，防止在控制电路中引起问题的噪声 变成路由并感应到输出缓冲区。 更具体地，可以通过以下两种方法之一来实现上述：（A）为控制电路提供片上旁路电容器，并将控制电路的馈电路径与AC类似的输出缓冲器的馈电路径隔离 方式或（B）设计电参数（插入电阻），使得引入馈电路径的任何电参数噪声的振荡模式将变为过阻尼。

    Semiconductor device
    10.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20060017144A1

    公开(公告)日：2006-01-26

    申请号：US10981676

    申请日：2004-11-05

    申请人： Yutaka Uematsu ,  Hideki Osaka ,  Yoji Nishio ,  Yukitoshi Hirose

    发明人： Yutaka Uematsu ,  Hideki Osaka ,  Yoji Nishio ,  Yukitoshi Hirose

    IPC分类号： H01L23/02

    CPC分类号： H01L23/642 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/5286 ,  H01L23/647 ,  H01L25/105 ,  H01L2224/73204 ,  H01L2924/19105 ,  H01L2924/3011

    摘要： The present invention provides a technique which, without causing two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.

    摘要翻译： 本发明提供一种技术，其不会引起两个问题，即（1）增加电源/接地引脚的数量和（2）增加的馈电线电感，防止在控制电路中引起问题的噪声变为布线 并引入输出缓冲区。 更具体地，可以通过以下两种方法之一来实现上述：（A）为控制电路提供片上旁路电容器，并将控制电路的馈电路径与AC类似的输出缓冲器的馈电路径隔离 方式或（B）设计电参数（插入电阻），使得引入馈电路径的任何电参数噪声的振荡模式将变为过阻尼。