公开(公告)号：US07320908B2

公开(公告)日：2008-01-22

申请号：US11072103

申请日：2005-03-04

申请人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Jong-Wook Lee ,  In-Soo Jung ,  Deok-Hyung Lee

发明人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Jong-Wook Lee ,  In-Soo Jung ,  Deok-Hyung Lee

IPC分类号： H01L21/338

CPC分类号： H01L29/7851 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66621

摘要： Methods for forming semiconductor devices are provided. A semiconductor substrate is etched such that the semiconductor substrate defines a trench and a preliminary active pattern. The trench has a floor and a sidewall. An insulating layer is provided on the floor and the sidewall of the trench and a spacer is formed on the insulating layer such that the spacer is on the sidewall of the trench and on a portion of the floor of the trench. The insulating layer is removed on the floor of the trench and beneath the spacer such that a portion of the floor of the trench is at least partially exposed, the spacer is spaced apart from the floor of the trench and a portion of the preliminary active pattern is partially exposed. A portion of the exposed portion of the preliminary active pattern is partially removed to provide an active pattern that defines a recessed portion beneath the spacer. A buried insulating layer is formed in the recessed portion of the active pattern. Related devices are also provided.

摘要翻译： 提供了形成半导体器件的方法。 蚀刻半导体衬底，使得半导体衬底限定沟槽和初步活性图案。 沟槽具有地板和侧壁。 绝缘层设置在地板上，并且沟槽的侧壁和间隔件形成在绝缘层上，使得间隔件位于沟槽的侧壁和沟槽底部的一部分上。 绝缘层在沟槽的地板上移除并且在间隔物的下面被移除，使得沟槽的底部的一部分至少部分地露出，间隔物与沟槽的底部间隔开，并且预活性图案的一部分 部分暴露。 部分地去除预活性图案的暴露部分的一部分以提供在间隔物下方限定凹陷部分的活性图案。 在活性图案的凹部中形成掩埋绝缘层。 还提供了相关设备。

公开(公告)号：US08039350B2

公开(公告)日：2011-10-18

申请号：US12582073

申请日：2009-10-20

申请人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

发明人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7833

摘要： Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.

摘要翻译： 提供了具有升高的源极/漏极区域的金属氧化物半导体（MOS）晶体管的制造方法。 通过这些方法形成的MOS晶体管可以包括形成为跨越衬底的预定区域的栅极图案。 凹陷区域设置在与栅极图案相邻的衬底中。 外凹层设置在凹陷区域的底表面上。 在外延层中设置高浓度杂质区。 凹陷区域可以使用化学干蚀刻技术形成。

公开(公告)号：US07074662B2

公开(公告)日：2006-07-11

申请号：US10869764

申请日：2004-06-16

申请人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

发明人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

IPC分类号： H01L21/8238

CPC分类号： H01L29/7851 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795

摘要： A method of forming a fin field effect transistor on a semiconductor substrate includes forming a vertical fin protruding from the substrate. A buffer oxide liner is formed on a top surface and on sidewalls of the fin. A trench is then formed on the substrate, where at least a portion of the fin protrudes from a bottom surface of the trench. The trench may be formed by forming a dummy gate on at least a portion of the fin, forming an insulation layer on the fin surrounding the dummy gate, and then removing the dummy gate to expose the at least a portion of the fin, such that the trench is surrounded by the insulation layer. The buffer oxide liner is then removed from the protruding portion of the fin, and a gate is formed in the trench on the protruding portion of the fin.

摘要翻译： 在半导体衬底上形成鳍状场效应晶体管的方法包括形成从衬底突出的垂直翅片。 缓冲氧化物衬垫形成在翅片的顶表面和侧壁上。 然后在衬底上形成沟槽，其中鳍的至少一部分从沟槽的底表面突出。 可以通过在鳍片的至少一部分上形成伪栅极来形成沟槽，在围绕虚拟栅极的鳍片上形成绝缘层，然后去除伪栅极以暴露鳍片的至少一部分，使得 沟槽被绝缘层包围。 然后从鳍片的突出部分去除缓冲氧化物衬垫，并且在鳍片的突出部分上的沟槽中形成栅极。

公开(公告)号：US07494877B2

公开(公告)日：2009-02-24

申请号：US11691529

申请日：2007-03-27

申请人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

发明人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

IPC分类号： H01L21/8234

CPC分类号： H01L29/785 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/66553 ,  H01L29/66795

摘要： A method of forming a semiconductor device may include forming a fin structure extending from a substrate. The fin structure may include first and second source/drain regions and a channel region therebetween, and the first and second source/drain regions may extend a greater distance from the substrate than the channel region. A gate insulating layer may be formed on the channel region, and a gate electrode may be formed on the gate insulating layer so that the gate insulating layer is between the gate electrode and the channel region. Related devices are also discussed.

摘要翻译： 形成半导体器件的方法可以包括形成从衬底延伸的翅片结构。 翅片结构可以包括第一和第二源极/漏极区域和它们之间的沟道区域，并且第一和第二源极/漏极区域可以比沟道区域延伸比衬底更大的距离。 可以在沟道区上形成栅极绝缘层，并且可以在栅极绝缘层上形成栅电极，使得栅极绝缘层位于栅电极和沟道区之间。 还讨论了相关设备。

公开(公告)号：US20070190732A1

公开(公告)日：2007-08-16

申请号：US11691529

申请日：2007-03-27

申请人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

发明人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/66553 ,  H01L29/66795

摘要： A method of forming a semiconductor device may include forming a fin structure extending from a substrate. The fin structure may include first and second source/drain regions and a channel region therebetween, and the first and second source/drain regions may extend a greater distance from the substrate than the channel region. A gate insulating layer may be formed on the channel region, and a gate electrode may be formed on the gate insulating layer so that the gate insulating layer is between the gate electrode and the channel region. Related devices are also discussed.

摘要翻译： 形成半导体器件的方法可以包括形成从衬底延伸的翅片结构。 翅片结构可以包括第一和第二源极/漏极区域和它们之间的沟道区域，并且第一和第二源极/漏极区域可以比沟道区域延伸比衬底更大的距离。 可以在沟道区上形成栅极绝缘层，并且可以在栅极绝缘层上形成栅电极，使得栅极绝缘层位于栅电极和沟道区之间。 还讨论了相关设备。

公开(公告)号：US07205609B2

公开(公告)日：2007-04-17

申请号：US10853616

申请日：2004-05-25

申请人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

发明人： Deok-Hyung Lee ,  Si-Young Choi ,  Byeong-Chan Lee ,  Yong-Hoon Son ,  In-Soo Jung

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/66553 ,  H01L29/66795

摘要： A method of forming a semiconductor device may include forming a fin structure extending from a substrate. The fin structure may include first and second source/drain regions and a channel region therebetween, and the first and second source/drain regions may extend a greater distance from the substrate than the channel region. A gate insulating layer may be formed on the channel region, and a gate electrode may be formed on the gate insulating layer so that the gate insulating layer is between the gate electrode and the channel region. Related devices are also discussed.

摘要翻译： 形成半导体器件的方法可以包括形成从衬底延伸的翅片结构。 翅片结构可以包括第一和第二源极/漏极区域和它们之间的沟道区域，并且第一和第二源极/漏极区域可以比沟道区域延伸比衬底更大的距离。 可以在沟道区上形成栅极绝缘层，并且可以在栅极绝缘层上形成栅电极，使得栅极绝缘层位于栅电极和沟道区之间。 还讨论了相关设备。

公开(公告)号：US20070004107A1

公开(公告)日：2007-01-04

申请号：US11530651

申请日：2006-09-11

申请人： Deok-Hyung Lee ,  Byeong-Chan Lee ,  Si-Young Choi ,  Taek-Jung Kim ,  Yong-Hoon Son ,  In-Soo Jung

发明人： Deok-Hyung Lee ,  Byeong-Chan Lee ,  Si-Young Choi ,  Taek-Jung Kim ,  Yong-Hoon Son ,  In-Soo Jung

IPC分类号： H01L21/84

CPC分类号： H01L29/785 ,  H01L21/823412 ,  H01L21/823437 ,  H01L29/66803

摘要： Integrated circuit field effect transistors include an integrated circuit substrate and a fin that projects away from the integrated circuit substrate, extends along the integrated circuit substrate, and includes a top that is remote from the integrated circuit substrate. A channel region is provided in the fin that is doped a conductivity type and has a higher doping concentration of the conductivity type adjacent the top than remote from the top. A source region and a drain region are provided in the fin on opposite sides of the channel region, and an insulated gate electrode extends across the fin adjacent the channel region. Related fabrication methods also are described

摘要翻译： 集成电路场效应晶体管包括集成电路基板和远离集成电路基板突出的翅片，沿着集成电路基板延伸，并且包括远离集成电路基板的顶部。 沟道区域设置在散热片中，其掺杂有导电类型，并且具有比远离顶部更靠近顶部的导电类型的较高的掺杂浓度。 源极区域和漏极区域设置在沟道区域的相对侧上的鳍片中，并且绝缘栅极电极在与沟道区域相邻的鳍片上延伸。 还描述了相关的制造方法

公开(公告)号：US20060202270A1

公开(公告)日：2006-09-14

申请号：US11433942

申请日：2006-05-15

申请人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

发明人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L29/7851 ,  H01L21/823431 ,  H01L27/12 ,  H01L29/66795

摘要： A field effect transistor includes a vertical fin-shaped semiconductor active region having an upper surface and a pair of opposing sidewalls on a substrate, and an insulated gate electrode on the upper surface and opposing sidewalls of the fin-shaped active region. The insulated gate electrode includes a capping gate insulation layer having a thickness sufficient to preclude formation of an inversion-layer channel along the upper surface of the fin-shaped active region when the transistor is disposed in a forward on-state mode of operation. Related fabrication methods are also discussed.

摘要翻译： 场效应晶体管包括在衬底上具有上表面和一对相对侧壁的垂直鳍状半导体有源区，以及鳍状有源区的上表面和相对侧壁上的绝缘栅电极。 绝缘栅电极包括封盖栅极绝缘层，当晶体管处于正向导通状态工作模式时，其具有足以防止在鳍状有源区的上表面形成反型层通道的厚度。 还讨论了相关的制造方法。

公开(公告)号：US20050095795A1

公开(公告)日：2005-05-05

申请号：US10886167

申请日：2004-07-07

申请人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

发明人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

IPC分类号： H01L21/336 ,  H01L21/425 ,  H01L21/8242 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7833

摘要： Metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions and methods of fabricating the same are provided. The MOS transistors may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.

摘要翻译： 提供了具有升高的源极/漏极区域的金属氧化物半导体（MOS）晶体管及其制造方法。 MOS晶体管可以包括形成为跨越衬底的预定区域的栅极图案。 凹陷区域设置在与栅极图案相邻的衬底中。 外凹层设置在凹陷区域的底表面上。 在外延层中设置高浓度杂质区。 凹陷区域可以使用化学干蚀刻技术形成。

公开(公告)号：US08304318B2

公开(公告)日：2012-11-06

申请号：US13241311

申请日：2011-09-23

申请人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

发明人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7833

摘要： Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.

摘要翻译： 提供了具有升高的源极/漏极区域的金属氧化物半导体（MOS）晶体管的制造方法。 通过这些方法形成的MOS晶体管可以包括形成为跨越衬底的预定区域的栅极图案。 凹陷区域设置在与栅极图案相邻的衬底中。 外凹层设置在凹陷区域的底表面上。 在外延层中设置高浓度杂质区。 凹陷区域可以使用化学干蚀刻技术形成。