公开(公告)号：US07511334B2

公开(公告)日：2009-03-31

申请号：US11296397

申请日：2005-12-08

申请人： Yong-kyu Lee ,  Jeong-uk Han ,  Sung-taeg Kang ,  Jong-duk Lee ,  Byung-gook Park

发明人： Yong-kyu Lee ,  Jeong-uk Han ,  Sung-taeg Kang ,  Jong-duk Lee ,  Byung-gook Park

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/66833 ,  H01L29/7923

摘要： A twin-ONO-type SONOS memory includes a semiconductor substrate having a source region, a drain region and a channel region between the source and drain regions, twin silicon oxide-silicon nitride-silicon oxide (ONO) dielectric layers, a first ONO dielectric layer being on the channel region and the source region and as second ONO dielectric layer being on the channel region and the drain region, and a control gate on the channel region, between the twin ONO dielectric layers, the twin ONO dielectric layers extending along at least lower lateral sides of the control gate adjacent the channel region, wherein the twin ONO dielectric layers extend towards the source and drain regions further than the control gate.

摘要翻译： 双ONO型SONOS存储器包括具有源极区，漏极区和源极和漏极区之间的沟道区的半导体衬底，双氧化硅 - 氮化硅 - 氧化硅（ONO）电介质层，第一ONO电介质 在沟道区域和源极区域之间以及作为第二ONO电介质层位于沟道区域和漏极区域上的第一ONO介电层以及沟道区域上的控制栅极之间，在双ONO介电层之间，双ONO介电层沿着 邻近通道区域的控制栅极的最小下侧，其中双ONO电介质层朝着比控制栅极更远的源极和漏极区延伸。

公开(公告)号：US20060086953A1

公开(公告)日：2006-04-27

申请号：US11296397

申请日：2005-12-08

申请人： Yong-kyu Lee ,  Jeong-uk Han ,  Sung-taeg Kang ,  Jong-duk Lee ,  Byung-gook Park

发明人： Yong-kyu Lee ,  Jeong-uk Han ,  Sung-taeg Kang ,  Jong-duk Lee ,  Byung-gook Park

IPC分类号： H01L29/76 ,  H01L29/745

CPC分类号： H01L21/28282 ,  H01L29/66833 ,  H01L29/7923

摘要： A twin-ONO-type SONOS memory includes a semiconductor substrate having a source region, a drain region and a channel region between the source and drain regions, twin silicon oxide-silicon nitride-silicon oxide (ONO) dielectric layers, a first ONO dielectric layer being on the channel region and the source region and as second ONO dielectric layer being on the channel region and the drain region, and a control gate on the channel region, between the twin ONO dielectric layers, the twin ONO dielectric layers extending along at least lower lateral sides of the control gate adjacent the channel region, wherein the twin ONO dielectric layers extend towards the source and drain regions further than the control gate.

公开(公告)号：US07005349B2

公开(公告)日：2006-02-28

申请号：US10781761

申请日：2004-02-20

申请人： Yong-kyu Lee ,  Jeong-uk Han ,  Sung-taeg Kang ,  Jong-duk Lee ,  Byung-gook Park

发明人： Yong-kyu Lee ,  Jeong-uk Han ,  Sung-taeg Kang ,  Jong-duk Lee ,  Byung-gook Park

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/66833 ,  H01L29/7923

摘要： A method of manufacturing a twin-ONO-type SONOS memory using a reverse self-alignment process, wherein an ONO dielectric layer is formed under a gate and physically separated into two portions using a reverse self-alignment process irrespective of photolithographic limits. To facilitate the reverse self-alignment, a buffer layer and spacers for defining the width of the ONO dielectric layer are adopted. Thus, the dispersion of trapped charges during programming and erasing can be appropriately adjusted, thus improving the characteristics of the SONOS. The present invention prevents the redistribution of charges in time after the programming and erasing operations.

摘要翻译： 使用反向自对准工艺制造双ONO型SONOS存储器的方法，其中在栅极下形成ONO电介质层，并且使用反向自对准工艺物理地分离成两部分，而与光刻极限无关。 为了促进反向自对准，采用用于限定ONO介电层宽度的缓冲层和间隔物。 因此，可以适当地调整编程和擦除期间的捕获电荷的分散，从而改善SONOS的特性。 本发明防止在编程和擦除操作之后的时间内重新分配电荷。

公开(公告)号：US20050255669A1

公开(公告)日：2005-11-17

申请号：US11095569

申请日：2005-04-01

申请人： Sung-taeg Kang ,  Jeong-uk Han ,  Sung-woo Park

发明人： Sung-taeg Kang ,  Jeong-uk Han ,  Sung-woo Park

IPC分类号： H01L21/76 ,  B81C1/00 ,  H01L21/762 ,  H01L21/8234

CPC分类号： H01L21/76224 ,  H01L21/823481

摘要： Provided is a trench isolation for a semiconductor device. The device includes an insulating layer formed on the inner surface of a trench and includes at least an N-containing CVD oxide layer, and a nitride liner formed on the insulating layer.

摘要翻译： 提供了半导体器件的沟槽隔离。 该器件包括形成在沟槽的内表面上的绝缘层，并且至少包含含N的CVD氧化物层和形成在绝缘层上的氮化物衬垫。

公开(公告)号：US06794711B2

公开(公告)日：2004-09-21

申请号：US10620025

申请日：2003-07-14

申请人： Sung-taeg Kang ,  Jeong-uk Han ,  Soeng-gyun Kim

发明人： Sung-taeg Kang ,  Jeong-uk Han ,  Soeng-gyun Kim

IPC分类号： H01L29788

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

摘要： Non-volatile memory devices according to embodiments of the invention can include, for example, a semiconductor substrate, a source region, a drain region, an impurity region, a vertical structure, a control gate insulating layer, a control gate electrode, a gate insulating layer, and a gate electrode. The impurity region is in a floating state between the source region and the drain region. The vertical structure is formed of a tunneling layer, a charge trapping layer, and a blocking layer sequentially stacked between the source region and the impurity region. The control gate insulating layer is between the source region and the impurity region and adjacent to the vertical structure. The control gate electrode is formed on the vertical structure and the control gate insulating layer. The gate insulating layer is between the impurity region and the drain region. The gate electrode is formed on the gate insulating layer.

摘要翻译： 根据本发明的实施例的非易失性存储器件可以包括例如半导体衬底，源极区，漏极区，杂质区，垂直结构，控制栅极绝缘层，控制栅电极，栅极 绝缘层和栅电极。 杂质区域在源极区域和漏极区域之间处于浮置状态。 垂直结构由依次层叠在源极区域和杂质区域之间的隧道层，电荷俘获层和阻挡层形成。 控制栅极绝缘层位于源极区域和杂质区域之间并且与垂直结构相邻。 控制栅电极形成在垂直结构和控制栅极绝缘层上。 栅极绝缘层位于杂质区域和漏极区域之间。 栅电极形成在栅绝缘层上。

公开(公告)号：US07928492B2

公开(公告)日：2011-04-19

申请号：US11804329

申请日：2007-05-17

申请人： Hee-seog Jeon ,  Jeong-uk Han ,  Hyun-khe Yoo ,  Yong-kyu Lee

发明人： Hee-seog Jeon ,  Jeong-uk Han ,  Hyun-khe Yoo ,  Yong-kyu Lee

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A non-volatile memory integrated circuit device and a method fabricating the same are disclosed. The non-volatile memory integrated circuit device includes a semiconductor substrate, word and select lines, and a floating junction region, a bit line junction region and a common source region. The semiconductor substrate has a plurality of substantially rectangular field regions, and the short and long sides of each substantially rectangular field region are parallel to the row and column directions of a matrix, respectively. The word lines and select lines extend parallel to the row direction on the semiconductor substrate, the word lines crossing a plurality of substantially rectangular field regions disposed in the row direction, and the select lines partially overlapping substantially rectangular field regions arranged in the row direction of the matrix, such that the parts of the long sides of the substantially field regions and the short sides of the substantially rectangular field regions are located below the select lines. The floating junction region is formed within the semiconductor substrate between the word lines and the select lines, the bit line junction region is formed opposite the floating junction region, and the common source region is formed opposite the floating junction region.

摘要翻译： 公开了一种非易失性存储器集成电路器件及其制造方法。 非易失性存储器集成电路器件包括半导体衬底，字和选择线，以及浮置结区域，位线接合区域和公共源极区域。 半导体衬底具有多个基本上矩形的场区域，并且每个大致矩形场区域的短边和长边分别平行于矩阵的行和列方向。 字线和选择线在半导体衬底上平行于行方向延伸，字线与沿行方向设置的多个基本上矩形的场区交叉，并且选择线部分地重叠大致矩形的场区域 矩阵，使得基本上场区域的长边的部分和基本上矩形的场区域的短边位于选择线下方。 在半导体衬底之间，在字线和选择线之间形成浮点结区，与浮置结区相对地形成位线结区域，并且与浮接区相对地形成公共源区。

公开(公告)号：US20070267684A1

公开(公告)日：2007-11-22

申请号：US11804329

申请日：2007-05-17

申请人： Hee-seog Jeon ,  Jeong-uk Han ,  Hyun-khe Yoo ,  Yong-kyu Lee

发明人： Hee-seog Jeon ,  Jeong-uk Han ,  Hyun-khe Yoo ,  Yong-kyu Lee

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A non-volatile memory integrated circuit device and a method fabricating the same are disclosed. The non-volatile memory integrated circuit device includes a semiconductor substrate, word and select lines, and a floating junction region, a bit line junction region and a common source region. The semiconductor substrate has a plurality of substantially rectangular field regions, and the short and long sides of each substantially rectangular field region are parallel to the row and column directions of a matrix, respectively. The word lines and select lines extend parallel to the row direction on the semiconductor substrate, the word lines crossing a plurality of substantially rectangular field regions disposed in the row direction, and the select lines partially overlapping substantially rectangular field regions arranged in the row direction of the matrix, such that the parts of the long sides of the substantially field regions and the short sides of the substantially rectangular field regions are located below the select lines. The floating junction region is formed within the semiconductor substrate between the word lines and the select lines, the bit line junction region is formed opposite the floating junction region, and the common source region is formed opposite the floating junction region.

摘要翻译： 公开了一种非易失性存储器集成电路器件及其制造方法。 非易失性存储器集成电路器件包括半导体衬底，字和选择线，以及浮置结区域，位线接合区域和公共源极区域。 半导体衬底具有多个基本上矩形的场区域，并且每个大致矩形场区域的短边和长边分别平行于矩阵的行和列方向。 字线和选择线在半导体衬底上平行于行方向延伸，字线与沿行方向设置的多个基本上矩形的场区交叉，并且选择线部分地重叠大致矩形的场区域 矩阵，使得基本上场区域的长边的部分和基本上矩形的场区域的短边位于选择线下方。 在半导体衬底之间，在字线和选择线之间形成浮点结区，与浮置结区相对地形成位线结区域，并且与浮接区相对地形成公共源极区。

公开(公告)号：US20100103744A1

公开(公告)日：2010-04-29

申请号：US12588680

申请日：2009-10-23

申请人： Seung-jin Yang ,  Jeong-uk Han ,  Yong-tae Kim ,  Yong-suk Choi ,  Bae-seong Kwon

发明人： Seung-jin Yang ,  Jeong-uk Han ,  Yong-tae Kim ,  Yong-suk Choi ,  Bae-seong Kwon

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/0433

摘要： A non-volatile memory device includes a memory cell array with a plurality of unit memory cells arranged in a matrix pattern, each of the unit memory cells having first and second non-volatile memory transistors sharing a common source, and a selection transistor connected between the common source and one of the first and second non-volatile memory transistors, a first word line coupled to control gates of the first non-volatile memory transistors arranged in a column direction of the memory cell array, a second word line coupled to control gates of the second non-volatile memory transistors arranged in the column direction of the memory cell array, a selection line coupled to gates of the selected transistors arranged in the column direction of the memory cell array, and at least one bit line coupled to drains of the first and second non-volatile memory transistors.

摘要翻译： 一种非易失性存储器件包括具有以矩阵模式布置的多个单元存储单元的存储单元阵列，每个单元存储单元具有共享公共源的第一和第二非易失性存储器晶体管，以及连接在 公共源和第一和第二非易失性存储器晶体管中的一个，耦合到以存储单元阵列的列方向布置的第一非易失性存储器晶体管的控制栅极的第一字线，耦合到控制的第二字线 布置在存储单元阵列的列方向上的第二非易失性存储晶体管的栅极，耦合到沿着存储单元阵列的列方向布置的所选晶体管的栅极的选择线以及耦合到漏极的至少一个位线 的第一和第二非易失性存储器晶体管。

公开(公告)号：US20080142869A1

公开(公告)日：2008-06-19

申请号：US11987294

申请日：2007-11-29

申请人： Kong-Sam Jang ,  Jeong-uk Han ,  Yong-tae Kim ,  Weon-ho Park

发明人： Kong-Sam Jang ,  Jeong-uk Han ,  Yong-tae Kim ,  Weon-ho Park

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7885 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42328

摘要： Example embodiments relate to a non-volatile memory device and a method of forming the same. A non-volatile memory device according to example embodiments may include a conductive pattern provided on the semiconductor substrate. A tunnel insulator may be provided on the conductive pattern. A memory gate structure may be provided on the semiconductor substrate so as to cover a first end of the conductive pattern. The first end may include an upward tapering, first protrusion. A select gate structure may be provided on the semiconductor substrate so as to cover the second end of the conductive pattern. The second end may include an upward tapering, second protrusion. The coverage of the first protrusion by the memory gate structure may be greater than the coverage of the second protrusion by the select gate structure.

摘要翻译： 示例性实施例涉及非易失性存储器件及其形成方法。 根据示例性实施例的非易失性存储器件可以包括设置在半导体衬底上的导电图案。 隧道绝缘体可以设置在导电图案上。 可以在半导体衬底上提供存储栅结构，以便覆盖导电图案的第一端。 第一端可包括向上逐渐变细的第一突起。 可以在半导体衬底上设置选择栅极结构，以覆盖导电图案的第二端。 第二端可以包括向上渐缩的第二突起。 通过存储器栅极结构的第一突起的覆盖可以大于通过选择栅极结构的第二突起的覆盖。

公开(公告)号：US20080087938A1

公开(公告)日：2008-04-17

申请号：US11905629

申请日：2007-10-03

申请人： Hee-seog Jeon ,  Jeong-uk Han

发明人： Hee-seog Jeon ,  Jeong-uk Han

IPC分类号： H01L27/115 ,  H01L27/112 ,  H01L21/8247

CPC分类号： H01L27/11253 ,  G11C11/005 ,  G11C16/0433 ,  G11C17/12 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11529

摘要： Example embodiments are directed to a mask ROM, a mask ROM embedded EEPROM and a method of fabricating the same. The mask ROM may include a select gate pattern and a memory gate pattern disposed between a source region and a drain region at each of the on-cell and the off-cell. The on-cell may include a cell diffusion region between the select gate pattern and the memory gate pattern.

摘要翻译： 示例性实施例涉及掩模ROM，掩模ROM嵌入式EEPROM及其制造方法。 掩模ROM可以包括选择栅极图案和布置在每个开孔单元和关闭单元之间的源区域和漏极区域之间的存储器栅极图案。 接通单元可以包括选择栅极图案和存储器栅极图案之间的单元扩散区域。