公开(公告)号：US06482699B1

公开(公告)日：2002-11-19

申请号：US09685972

申请日：2000-10-10

申请人： YongZhong Hu ,  Fei Wang ,  Wenge Yang ,  Yu Sun ,  Ramkumar Subramanian

发明人： YongZhong Hu ,  Fei Wang ,  Wenge Yang ,  Yu Sun ,  Ramkumar Subramanian

IPC分类号： H01L21336

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L2924/3011

摘要： A method of manufacturing a semiconductor device is provided in which multi-layer structures are formed on a semiconductor substrate to form core and peripheral regions. Sidewall spacers are formed around the multi-layer structures and source and drain regions are implanted adjacent the sidewall spacers and a stop layer is deposited over the semiconductor substrate after which a dielectric layer is deposited over the stop layer. A first and second photoresist contact masks are deposited, processed, and used to respectively etch core and peripheral contact openings. The first and photoresist contact masks are respectively removed after each etching step. A conductive material is deposited over the dielectric layer and in the core and peripheral contact openings and is chemical mechanical planarized to remove the conductive material over the dielectric layer so the conductive material is left isolated in the core and peripheral contact openings with core contacts to the source/drain regions and peripheral contacts to the local interconnect gate contacts of the multi-layer structures and the source/drain regions.

摘要翻译： 提供一种制造半导体器件的方法，其中在半导体衬底上形成多层结构以形成芯和周边区域。 在多层结构周围形成侧壁间隔物，并且将源极和漏极区域相邻于侧壁间隔物注入，并且在半导体衬底上沉积停止层，之后在停止层上沉积电介质层。 第一和第二光致抗蚀剂接触掩模被沉积，处理并用于分别蚀刻芯部和外围接触开口。 在每个蚀刻步骤之后分别去除第一和光致抗蚀剂接触掩模。 导电材料沉积在电介质层上以及芯和外围接触开口中，并进行化学机械平面化以去除电介质层上的导电材料，因此导电材料在核心和外围接触开口中被隔离，其核心接触到 源极/漏极区域和周边接触到多层结构和源极/漏极区域的局部互连栅极触点。

公开(公告)号：US06348406B1

公开(公告)日：2002-02-19

申请号：US09586264

申请日：2000-05-31

申请人： Ramkumar Subramanian ,  Minh Van Ngo ,  Kashmir Sahota ,  Yongzhong Hu ,  Hiroyuki Kinoshita ,  Fei Wang ,  Wenge Yang

发明人： Ramkumar Subramanian ,  Minh Van Ngo ,  Kashmir Sahota ,  Yongzhong Hu ,  Hiroyuki Kinoshita ,  Fei Wang ,  Wenge Yang

IPC分类号： H01L214763

CPC分类号： H01L27/11521 ,  H01L21/31144

摘要： The present invention provides a method for manufacturing a semiconductor device with an anti-reflective coating (ARC) that does not need to be removed. In one embodiment, electrical devices are formed on a semiconductor substrate. A dielectric layer is then deposited over the electrical devices and the semiconductor substrate, upon which an optically transparent ARC layer of low dielectric constant is then deposited. Photoresist is then deposited on top of the ARC layer and is then photolithographically processed and subsequently developed. The dielectric layer is then etched down to the semiconductor substrate to form contacts or local interconnects. The ARC layer can subsequently be used as a hard mask and does not require removal.

摘要翻译： 本发明提供一种制造具有不需要去除的抗反射涂层（ARC）的半导体器件的方法。 在一个实施例中，电子器件形成在半导体衬底上。 然后将电介质层沉积在电气器件和半导体衬底上，然后沉积出具有低介电常数的光学透明ARC层。 然后将光致抗蚀剂沉积在ARC层的顶部上，然后光刻加工并随后显影。 然后将电介质层向下蚀刻到半导体衬底以形成接触或局部互连。 ARC层可以随后用作硬掩模，并且不需要去除。

公开(公告)号：US06376389B1

公开(公告)日：2002-04-23

申请号：US09588117

申请日：2000-05-31

申请人： Ramkumar Subramanian ,  Minh Van Ngo ,  Kashmir Sahota ,  Yongzhong Hu ,  Hiroyuki Kinoshita ,  Fei Wang ,  Wenge Yang

发明人： Ramkumar Subramanian ,  Minh Van Ngo ,  Kashmir Sahota ,  Yongzhong Hu ,  Hiroyuki Kinoshita ,  Fei Wang ,  Wenge Yang

IPC分类号： H01L2100

CPC分类号： H01L21/76802 ,  H01L21/76895 ,  H01L23/522 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method for manufacturing a semiconductor device without the use of an anti-reflective coating. In one embodiment, electrical devices are formed on a semiconductor substrate. A material with a low dielectric constant such as an oxide is then deposited. The low dielectric layer is then covered with photoresist and photolithographically processed and subsequently developed. The low dielectric layer is then etched using the pattern formed on the photoresist and the photoresist is later removed. Because this process works in any similar circumstances, good examples of its application are the formation of both contacts and local interconnects.

摘要翻译： 本发明提供一种不使用抗反射涂层的半导体器件的制造方法。 在一个实施例中，电子器件形成在半导体衬底上。 然后沉积具有低介电常数的材料，例如氧化物。 然后用光致抗蚀剂覆盖低介电层，并进行光刻处理并随后显影。 然后使用形成在光致抗蚀剂上的图案蚀刻低介电层，随后去除光致抗蚀剂。 因为这个过程在任何类似的情况下都可以工作，它的应用的很好的例子是形成两个触点和局部互连。

公开(公告)号：US06306713B1

公开(公告)日：2001-10-23

申请号：US09799469

申请日：2001-03-05

申请人： YongZhong Hu ,  Fei Wang ,  Wenge Yang ,  Yu Sun ,  Hiroyuki Kinoshita

发明人： YongZhong Hu ,  Fei Wang ,  Wenge Yang ,  Yu Sun ,  Hiroyuki Kinoshita

IPC分类号： H01L21336

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L2924/3011

摘要： A method of manufacturing a semiconductor device is provided in which multi-layer structures are formed on a semiconductor substrate to form core and peripheral regions. Sidewall spacers are formed around the multi-layer structures and source and drain regions are implanted adjacent the sidewall spacers. The multi-layer structures and the source and drain regions are silicided and a stop layer is deposited over the semiconductor substrate after which a dielectric layer is deposited over the stop layer. A photoresist contact mask is deposited, processed, and used to form core contact openings over the core region, which expose the multi-layer structure in addition to the source and drain regions while covering the peripheral region. Protective secondary sidewall spacers are formed in the core contact openings over the exposed multi-layer structures. A second photoresist contact mask is deposited, processed, and used to form peripheral local interconnect openings over the peripheral region which the source and drain regions and portions of the plurality of multi-layer structures in the peripheral region while covering the core region. A conductive material is deposited over the dielectric layer and in the core contact and peripheral local interconnect openings and is chemical mechanical planarized to remove the conductive material over the dielectric layer so the conductive material is left isolated in the core and peripheral contact openings.

摘要翻译： 提供一种制造半导体器件的方法，其中在半导体衬底上形成多层结构以形成芯和周边区域。 围绕多层结构形成侧壁间隔物，并且将源极和漏极区域相邻于侧壁间隔物注入。 多层结构和源极和漏极区域被硅化，并且在半导体衬底上沉积停止层，之后在停止层上沉积电介质层。 光致抗蚀剂接触掩模被沉积，加工并用于在芯部区域上形成芯接触开口，除了覆盖周边区域之外，还暴露多层结构以及源极和漏极区域。 保护性次级侧壁间隔件形成在暴露的多层结构上的芯接触开口中。 第二光致抗蚀剂接触掩模被沉积，加工并用于在外围区域上形成周边局部互连开口，周边区域是外围区域的源极和漏极区域以及多个多层结构的部分，同时覆盖芯部区域。 导电材料沉积在电介质层上，并在芯接触和外围局部互连开口中沉积，并进行化学机械平面化以去除电介质层上的导电材料，使得导电材料在芯和外围接触开口中被隔离。

公开(公告)号：US06878622B1

公开(公告)日：2005-04-12

申请号：US10612554

申请日：2003-07-01

申请人： Wenge Yang ,  Ramkumar Subramanian ,  Fei Wang ,  Lewis Shen

发明人： Wenge Yang ,  Ramkumar Subramanian ,  Fei Wang ,  Lewis Shen

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/60 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/44

CPC分类号： H01L21/76897 ,  H01L21/0276 ,  H01L21/31116 ,  H01L2924/3011

摘要： A method is provided for manufacturing a semiconductor device on a semiconductor substrate using a dielectric as a bottom anti-reflective coating for formation of a photoresist contact opening which is used to enlarge the Final Inspection Critical Dimension (FICD) of the conductive contact. A high selectivity etch is used to form a tapered contact.

摘要翻译： 提供了一种用于在半导体衬底上制造半导体器件的方法，该半导体衬底使用电介质作为用于形成光刻胶接触开口的底部抗反射涂层，用于扩大导电触点的最终检查临界尺寸（FICD）。 使用高选择性蚀刻来形成锥形接触。

公开(公告)号：US06271087B1

公开(公告)日：2001-08-07

申请号：US09685968

申请日：2000-10-10

申请人： Hiroyuki Kinoshita ,  YongZhong Hu ,  Yu Sun ,  Fei Wang

发明人： Hiroyuki Kinoshita ,  YongZhong Hu ,  Yu Sun ,  Fei Wang

IPC分类号： H01L21336

CPC分类号： H01L21/76897 ,  H01L21/31144 ,  H01L21/76895 ,  H01L2924/3011

摘要： A method of manufacturing a semiconductor device is provided in which multi-layer structures are formed on a semiconductor substrate to form core and peripheral regions. Sidewall spacers are formed around the multi-layer structures and source and drain regions are implanted adjacent the sidewall spacers and a stop layer is deposited over the semiconductor substrate after which a dielectric layer is deposited over the stop layer. A first photoresist contact mask is deposited, processed, and used to etch core contact and peripheral local interconnect openings. The first photoresist contact mask is removed. A second photoresist contact mask is deposited, processed, and used to etch the multi-layer structures to form local interconnect openings. The second photoresist contact mask is removed. A conductive material is deposited over the dielectric layer and in the core and peripheral contact openings and is chemical mechanical planarized to remove the conductive material over the dielectric layer so the conductive material is left isolated in the core contact and peripheral local interconnect openings with core contacts to the source/drain regions and peripheral local interconnect contacts to the multi-layer structures and the source/drain regions.

摘要翻译： 提供一种制造半导体器件的方法，其中在半导体衬底上形成多层结构以形成芯和周边区域。 在多层结构周围形成侧壁间隔物，并且将源极和漏极区域相邻于侧壁间隔物注入，并且在半导体衬底上沉积停止层，之后在停止层上沉积电介质层。 第一光致抗蚀剂接触掩模被沉积，处理并用于蚀刻芯接触和外围局部互连开口。 去除第一光致抗蚀剂接触掩模。 沉积，处理和用于蚀刻多层结构以形成局部互连开口的第二光致抗蚀剂接触掩模。 去除第二光致抗蚀剂接触掩模。 导电材料沉积在电介质层上，并在芯和外围接触开口中沉积，并进行化学机械平面化以去除电介质层上的导电材料，因此导电材料在芯接触区和外围局部互连开口处与芯触点隔离 到源极/漏极区域和外围局部互连触点到多层​​结构和源极/漏极区域。

公开(公告)号：US06509229B1

公开(公告)日：2003-01-21

申请号：US09850484

申请日：2001-05-07

申请人： Fei Wang ,  Ramkumar Subramanian ,  Yu Sun

发明人： Fei Wang ,  Ramkumar Subramanian ,  Yu Sun

IPC分类号： H01L21336

CPC分类号： H01L21/76897 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L2924/3011

摘要： A method for shrinking a semiconductor device is disclosed. An etch stop layer is eliminated and is replaced with a consumable second sidewall spacers so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. In a preferred embodiment, the present invention provides a method for forming self-aligned contacts by forming multi-layer structures on a region on a semiconductor substrate, forming first sidewall spacers around the multi-layer structures, forming second sidewall spacers around the first sidewall spacers, forming a dielectric layer directly over the substrate and in contact with second sidewall spacers, forming an opening in the dielectric layer to expose a portion of the region on the semiconductor substrate adjacent the second sidewall spacers, and filling the opening with a conductive material to form a contact.

摘要翻译： 公开了一种用于收缩半导体器件的方法。 消除了蚀刻停止层，并且被可消耗的第二侧壁间隔物代替，使得该器件的堆叠栅极结构可以更靠近地放置在一起，从而允许器件收缩。 在优选实施例中，本发明提供了一种通过在半导体衬底上的区域上形成多层结构来形成自对准接触的方法，在多层结构周围形成第一侧墙，围绕第一侧壁形成第二侧壁 间隔物，直接在衬底上形成电介质层并与第二侧壁间隔物接触，在电介质层中形成开口以暴露与第二侧壁间隔物相邻的半导体衬底上的区域的一部分，并用导电材料填充该开口 形成联系。

公开(公告)号：US06348379B1

公开(公告)日：2002-02-19

申请号：US09502153

申请日：2000-02-11

申请人： Fei Wang ,  Ramkumar Subramanian ,  Yu Sun

发明人： Fei Wang ,  Ramkumar Subramanian ,  Yu Sun

IPC分类号： H01L21336

CPC分类号： H01L21/76897 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L2924/3011

摘要： A method for shrinking a semiconductor device is disclosed. An etch stop layer is eliminated and is replaced with a consumable second sidewall spacers so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. In a preferred embodiment, the present invention provides a method for forming self-aligned contacts by forming multi-layer structures on a region on a semiconductor substrate, forming first sidewall spacers around the multi-layer structures, forming second sidewall spacers around the first sidewall spacers, forming a dielectric layer directly over the substrate and in contact with second sidewall spacers, forming an opening in the dielectric layer to expose a portion of the region on the semiconductor substrate adjacent the second sidewall spacers, and filling the opening with a conductive material to form a contact.

摘要翻译： 公开了一种用于收缩半导体器件的方法。 消除了蚀刻停止层，并且被可消耗的第二侧壁间隔物代替，使得该器件的堆叠栅极结构可以更靠近地放置在一起，从而允许器件收缩。 在优选实施例中，本发明提供了一种通过在半导体衬底上的区域上形成多层结构来形成自对准接触的方法，在多层结构周围形成第一侧墙，围绕第一侧壁形成第二侧壁 间隔物，直接在衬底上形成电介质层并与第二侧壁间隔物接触，在电介质层中形成开口以暴露与第二侧壁间隔物相邻的半导体衬底上的区域的一部分，并用导电材料填充该开口 形成联系。

公开(公告)号：US06359307B1

公开(公告)日：2002-03-19

申请号：US09493436

申请日：2000-01-29

申请人： Fei Wang ,  Hiroyuki Kinoshita ,  Kashmir Sahota ,  Yu Sun ,  Wenge Yang

发明人： Fei Wang ,  Hiroyuki Kinoshita ,  Kashmir Sahota ,  Yu Sun ,  Wenge Yang

IPC分类号： H01L2976

CPC分类号： H01L21/76897 ,  H01L23/485 ,  H01L27/115 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y02P80/30 ,  H01L2924/00

摘要： The present invention further provides a method for forming self-aligned contacts using a dual damascene techniques that reduces the number of process steps and results in a reduction in cycle time, cost and yield loss. In a preferred embodiment, a method for forming a contact and a channel in a dielectric layer over a region on a semiconductor substrate is provided. The contact is self-aligned. The contact and channel are formed by (1) forming a contact opening in the dielectric layer, (2) forming a channel opening in the dielectric layer, wherein the channel opening encompasses the contact opening, (3) extending the contact opening to expose a portion of the region on the semiconductor substrate; and (4) filling the contact opening and the channel opening with a conductive material to form a contact and a channel, respectively.

摘要翻译： 本发明还提供了一种使用双镶嵌技术形成自对准接触的方法，其减少了工艺步骤的数量并导致了循环时间，成本和屈服损失的降低。 在优选实施例中，提供了在半导体衬底上的区域上形成电介质层中的接触和沟道的方法。 联系人自行对齐。 接触和通道由（1）在电介质层中形成接触开口形成，（2）在电介质层中形成通道开口，其中通道开口包围接触开口，（3）延伸接触开口以露出 所述半导体衬底上的所述区域的部分; 和（4）分别用导电材料填充接触开口和通道开口以形成接触和通道。

公开(公告)号：US06391766B1

公开(公告)日：2002-05-21

申请号：US09788641

申请日：2001-02-21

申请人： Fei Wang ,  Lynne A. Okada ,  Ramkumar Subramanian ,  Calvin T. Gabriel

发明人： Fei Wang ,  Lynne A. Okada ,  Ramkumar Subramanian ,  Calvin T. Gabriel

IPC分类号： H01L214763

CPC分类号： H01L21/76835 ,  H01L21/76808 ,  H01L2221/1031

摘要： A method of forming an interconnect structure in which an organic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to form a slot via in the first dielectric layer. The slot via is longer than the width of a subsequently formed trench. An inorganic low k dielectric material is deposited within the slot via and over the etch stop layer to form a second dielectric layer over the slot via and the etch stop layer. The re-filled slot via is simultaneously etched with the second dielectric layer in which a trench is formed. The entire width of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.

摘要翻译： 一种形成互连结构的方法，其中有机低k介电材料沉积在导电层上以形成第一介电层。 在第一电介质层上形成蚀刻停止层。 蚀刻停止层和第一介电层被蚀刻以在第一介电层中形成槽通孔。 狭缝通孔比随后形成的沟槽的宽度长。 无机低k介电材料通过蚀刻停止层上方和上方沉积在槽内，以在槽通孔和蚀刻停止层上形成第二电介质层。 再填充的槽通孔与其中形成沟槽的第二电介质层同时蚀刻。 沟槽的整个宽度直接在通孔上方。 重新打开的通孔和沟槽填充有导电材料。