公开(公告)号：US07746718B2

公开(公告)日：2010-06-29

申请号：US11998428

申请日：2007-11-30

申请人： Yasuyuki Eguchi ,  Shinya Fujioka ,  Yoshiaki Okuyama

发明人： Yasuyuki Eguchi ,  Shinya Fujioka ,  Yoshiaki Okuyama

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C8/12 ,  G11C11/40622

摘要： A refresh register stores disable block information indicating a memory block whose refresh operation is to be disabled. A refresh control circuit periodically executes the refresh operation of a memory block except the memory block corresponding to the disable block information. During an access cycle to one of the memory blocks, the register control circuit writes the disable block information to the refresh register according to an external input. Consequently, in order to rewrite the refresh register, it is not necessary to use an additional operation cycle to the access cycle. Since there is no need to insert an extra operation cycle, it is possible to change a memory area to be refreshed without lowering effective efficiency of access cycles. As a result, power consumption can be reduced.

摘要翻译： 刷新寄存器存储指示将被禁用刷新操作的存储器块的禁止块信息。 刷新控制电路周期性地执行除了与禁用块信息相对应的存储块之外的存储器块的刷新操作。 在对存储器块之一的访问周期期间，寄存器控制电路根据外部输入将该禁止块信息写入刷新寄存器。 因此，为了重写刷新寄存器，不需要对访问周期使用附加的操作周期。 由于不需要插入额外的操作周期，因此可以改变要刷新的存储器区域，而不会降低访问周期的有效效率。 结果，可以降低功耗。

公开(公告)号：US20080144417A1

公开(公告)日：2008-06-19

申请号：US11998428

申请日：2007-11-30

申请人： Yasuyuki Eguchi ,  Shinya Fujioka ,  Yoshiaki Okuyama

发明人： Yasuyuki Eguchi ,  Shinya Fujioka ,  Yoshiaki Okuyama

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/406 ,  G11C8/12 ,  G11C11/40622

摘要： A refresh register stores disable block information indicating a memory block whose refresh operation is to be disabled. A refresh control circuit periodically executes the refresh operation of a memory block except the memory block corresponding to the disable block information. During an access cycle to one of the memory blocks, the register control circuit writes the disable block information to the refresh register according to an external input. Consequently, in order to rewrite the refresh register, it is not necessary to use an additional operation cycle to the access cycle. Since there is no need to insert an extra operation cycle, it is possible to change a memory area to be refreshed without lowering effective efficiency of access cycles. As a result, power consumption can be reduced.

摘要翻译： 刷新寄存器存储指示将被禁用刷新操作的存储器块的禁止块信息。 刷新控制电路周期性地执行除了与禁用块信息相对应的存储块之外的存储器块的刷新操作。 在对存储器块之一的访问周期期间，寄存器控制电路根据外部输入将该禁止块信息写入刷新寄存器。 因此，为了重写刷新寄存器，不需要对访问周期使用附加的操作周期。 由于不需要插入额外的操作周期，因此可以改变要刷新的存储区域，而不会降低访问周期的有效效率。 结果，可以降低功耗。

公开(公告)号：US20060291307A1

公开(公告)日：2006-12-28

申请号：US11260486

申请日：2005-10-28

申请人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

发明人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

IPC分类号： G11C29/00

CPC分类号： G11C29/06 ,  G11C29/10 ,  G11C2029/0405 ,  G11C2029/1204 ,  G11C2029/3602

摘要： A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.

摘要翻译： 包括在每个步骤中施加相同时间长度的电压的第一至第六步骤的老化测试被施加到具有交替排列的位线对的半导体存储器，其中位线彼此交叉并且位线 对，其中位线彼此平行的非扭转结构。 由于可以对所有位线施加应力的时间长度，所以在位线之间施加应力的时间长度不会发生偏差。 可以防止记忆单元的特性从老化测试过度恶化。 此外，在第一至第六步骤中可以使不具有应力的位线的数量最小化。 因此，可以增加施加了应力的位线的比例，这降低了老化测试时间。 因此，可以降低测试成本。

公开(公告)号：US06847570B2

公开(公告)日：2005-01-25

申请号：US10300800

申请日：2002-11-21

申请人： Shinya Fujioka ,  Yoshiaki Okuyama

发明人： Shinya Fujioka ,  Yoshiaki Okuyama

IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1063 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076

摘要： A refresh control circuit generates a refresh request in a predetermined cycle. A first burst control circuit outputs a predetermined number of strobe signals in accordance with an access command. A burst access operation is executed by an access command. A data input/output circuit successively inputs data to be transferred to a memory cell array or successively outputs data supplied from the memory cell array, in synchronization with the strobe signals. An arbiter determines which of a refresh operation or a burst access operation is to be executed first, when the refresh request and the access command conflict with each other. Therefore, the refresh operation and burst access operation can be sequentially executed without being overlapped. As a result, read data can be outputted at a high speed, and write data can be inputted at a high speed. That is, the data transfer rate can be improved.

摘要翻译： 刷新控制电路以预定的周期生成刷新请求。 第一突发控制电路根据访问命令输出预定数量的选通信号。 通过访问命令执行突发存取操作。 数据输入/输出电路连续输入要传送到存储单元阵列的数据，或者与选通信号同步地连续输出从存储单元阵列提供的数据。 当刷新请求和访问命令彼此冲突时，仲裁器确定首先执行刷新操作或突发存取操作中的哪一个。 因此，可以顺序地执行刷新操作和突发存取操作而不重叠。 结果，可以高速地输出读取数据，并且可以高速地输入写入数据。 也就是说，可以提高数据传输速率。

公开(公告)号：US06621750B2

公开(公告)日：2003-09-16

申请号：US10155029

申请日：2002-05-28

申请人： Yoshiaki Okuyama ,  Shinya Fujioka ,  Kota Hara ,  Katsuhiro Mori

发明人： Yoshiaki Okuyama ,  Shinya Fujioka ,  Kota Hara ,  Katsuhiro Mori

IPC分类号： G11C700

CPC分类号： G11C29/808 ,  G11C29/812 ,  G11C29/848

摘要： A redundancy memory circuit stores a defect address indicating a defective memory cell row. A redundancy control circuit disables the defective memory cell row corresponding to the defect address stored in the redundancy memory circuit and enables a redundancy memory cell row in the memory block containing the defective memory cell row. Moreover, in the other memory blocks, the redundancy control circuit disables memory cell rows corresponding to the defective memory cell row and enables redundancy memory cell rows instead of these memory cell rows. Consequently, not only the memory block having the defective memory cell row but one of the memory cell rows in the other memory blocks is always also relieved. Thus, the redundancy memory circuit can be shared among all the memory blocks with a reduction in the number of redundancy memory circuits. As a result, the semiconductor memory can be reduced in chip size.

公开(公告)号：US07730232B2

公开(公告)日：2010-06-01

申请号：US11113181

申请日：2005-04-25

申请人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

发明人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

IPC分类号： G06F13/00

CPC分类号： G06F12/0804 ,  G06F2212/2022 ,  G11C7/1006 ,  G11C11/406 ,  G11C11/40615 ,  G11C16/06 ,  G11C16/3454

摘要： A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.

摘要翻译： 提供了一种数据传输方法和系统，其防止写入闪速存储器所需的时间长度出现在表面上，作为使用闪速存储器代替SRAM的系统操作。 传送数据的方法包括以下步骤：将数据从控制器写入易失性存储器，将易失性存储器置于传送状态，将数据从传送状态的易失性存储器传送到非易失性存储器，并将易失性存储器从 响应于确认完成数据传送的传送状态。

公开(公告)号：US07200059B2

公开(公告)日：2007-04-03

申请号：US11260486

申请日：2005-10-28

申请人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

发明人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

IPC分类号： G11C29/00

CPC分类号： G11C29/06 ,  G11C29/10 ,  G11C2029/0405 ,  G11C2029/1204 ,  G11C2029/3602

摘要： A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.

摘要翻译： 包括在每个步骤中施加相同时间长度的电压的第一至第六步骤的老化测试被施加到具有交替排列的位线对的半导体存储器，其中位线彼此交叉并且位线 对，其中位线彼此平行的非扭转结构。 由于可以对所有位线施加应力的时间长度，所以在位线之间施加应力的时间长度不会发生偏差。 可以防止记忆单元的特性从老化测试过度恶化。 此外，在第一至第六步骤中可以使不具有应力的位线的数量最小化。 因此，可以增加施加了应力的位线的比例，这降低了老化测试时间。 因此，可以降低测试成本。

公开(公告)号：US07050353B2

公开(公告)日：2006-05-23

申请号：US10994630

申请日：2004-11-23

申请人： Shinya Fujioka ,  Yoshiaki Okuyama

发明人： Shinya Fujioka ,  Yoshiaki Okuyama

IPC分类号： G11C8/00

CPC分类号： G11C7/1051 ,  G11C7/1063 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076

摘要： A refresh control circuit generates a refresh request in a predetermined cycle. A first burst control circuit outputs a predetermined number of strobe signals in accordance with an access command. A burst access operation is executed by an access command. A data input/output circuit successively inputs data to be transferred to a memory cell array or successively outputs data supplied from the memory cell array, in synchronization with the strobe signals. An arbiter determines which of a refresh operation or a burst access operation is to be executed first, when the refresh request and the access command conflict with each other. Therefore, the refresh operation and burst access operation can be sequentially executed without being overlapped. As a result, read data can be outputted at a high speed, and write data can be inputted at a high speed. That is, the data transfer rate can be improved.

摘要翻译： 刷新控制电路以预定的周期生成刷新请求。 第一突发控制电路根据访问命令输出预定数量的选通信号。 通过访问命令执行突发存取操作。 数据输入/输出电路连续输入要传送到存储单元阵列的数据，或者与选通信号同步地连续输出从存储单元阵列提供的数据。 当刷新请求和访问命令彼此冲突时，仲裁器确定首先执行刷新操作或突发存取操作中的哪一个。 因此，可以顺序地执行刷新操作和突发存取操作而不重叠。 结果，可以高速地输出读取数据，并且可以高速地输入写入数据。 也就是说，可以提高数据传输速率。

公开(公告)号：US20050185493A1

公开(公告)日：2005-08-25

申请号：US11113181

申请日：2005-04-25

申请人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

发明人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F13/16 ,  G11C7/10 ,  G11C8/00 ,  G11C11/406 ,  G11C16/12 ,  G11C16/34

CPC分类号： G06F12/0804 ,  G06F2212/2022 ,  G11C7/1006 ,  G11C11/406 ,  G11C11/40615 ,  G11C16/06 ,  G11C16/3454

摘要： A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.

摘要翻译： 提供了一种数据传输方法和系统，其防止写入闪速存储器所需的时间长度出现在表面上，作为使用闪速存储器代替SRAM的系统操作。 传送数据的方法包括以下步骤：将数据从控制器写入易失性存储器，将易失性存储器置于传送状态，将数据从传送状态的易失性存储器传送到非易失性存储器，并将易失性存储器从 响应于确认完成数据传送的传送状态。

公开(公告)号：US06404688B2

公开(公告)日：2002-06-11

申请号：US09791839

申请日：2001-02-26

申请人： Yoshiaki Okuyama ,  Yoshitaka Takahashi ,  Shinya Fujioka ,  Akihiro Funyu

发明人： Yoshiaki Okuyama ,  Yoshitaka Takahashi ,  Shinya Fujioka ,  Akihiro Funyu

IPC分类号： G11C700

CPC分类号： G11C11/406 ,  G11C7/1045

摘要： A semiconductor memory device having a self-refresh operation includes a first circuit generating a first signal that specifies a first self-refresh cycle by a non-volatile circuit element provided in the semiconductor memory device, a second circuit receiving a second signal that specifies a second self-refresh cycle via a terminal that is used in common to another signal, and a third circuit generating a pulse signal having one of the first and second self-refresh cycles, the pulse signal being related to the self-refresh operation.

摘要翻译： 具有自刷新操作的半导体存储器件包括：第一电路，产生由设置在半导体存储器件中的非易失性电路元件指定第一自刷新周期的第一信号;第二电路，接收指定第 第二自刷新周期经由与另一信号共同使用的端子，以及第三电路，产生具有第一和第二自刷新周期中的一个的脉冲信号，所述脉冲信号与自刷新操作相关。