公开(公告)号：US06566823B2

公开(公告)日：2003-05-20

申请号：US10019128

申请日：2001-12-27

申请人： Yoshihide Kinbara ,  Takashi Yuzawa ,  Hajime Ogawa

发明人： Yoshihide Kinbara ,  Takashi Yuzawa ,  Hajime Ogawa

IPC分类号： H05B4124

CPC分类号： H03K3/53 ,  B23H1/022 ,  B23H2300/20 ,  B23H2300/22

摘要： A discharge pulse generator for supplying power between a pair of electrodes (1 and 2), comprises a distribution constant line (8) of a predetermined length being connected at one termination to the electrodes (1 and 2), charging means (16) being connected to the distribution constant line (8) for charging the capacitance of the distribution constant line (8), rectification means (13) being connected to an opposite termination of the above-mentioned distribution constant line (8) in a direction in which no current flows relative to voltage of the above-mentioned charging means (16), and a resistor (10) being connected in series to the above-mentioned rectification means (13) and having a resistance value equal to the characteristic impedance of the above-mentioned distribution constant line (8). For example, to use the discharge pulse generator for electric discharge machining, a workpiece can be worked on with higher accuracy and higher quality at higher speed.

摘要翻译： 一种用于在一对电极（1和2）之间供电的放电脉冲发生器包括一个预定长度的分布常数线（8），其一端连接到电极（1和2），充电装置（16）为 连接到用于对分布常数线（8）的电容进行充电的分布常数线（8），整流装置（13）在不存在的方向上连接到上述分布常数线（8）的相反端子 电流相对于上述充电装置（16）的电压流动，并且电阻器（10）与上述整流装置（13）串联连接并且具有与上述充电装置（16）的特性阻抗相等的电阻值， 上述分布常数线（8）。 例如，为了使用放电脉冲发生器进行放电加工，可以以更高的速度以更高的精度和更高的质量加工工件。

公开(公告)号：US5539178A

公开(公告)日：1996-07-23

申请号：US151854

申请日：1993-11-15

申请人： Atsushi Taneda ,  Hajime Ogawa ,  Kazuhiko Uemoto ,  Yoshihide Kinbara

发明人： Atsushi Taneda ,  Hajime Ogawa ,  Kazuhiko Uemoto ,  Yoshihide Kinbara

IPC分类号： B23H1/02 ,  B23H1/00 ,  G05F1/40

CPC分类号： B23H1/022

摘要： In a power supply apparatus of an electrical discharge machine, a power supply high in efficiency and small in current ripple is provided to achieve a power supply reduced in size and price. In addition, a switching power supply system is used jointly to generate an optional waveform. A first switching device is switched on/off in an optional cycle under the control of a current command value signal corresponding to the waveform shape of a current pulse to be supplied to a machining gap, whereby an optional shape of current pulse is supplied to the machining gap and a current component which compensates for a current ripple generated by said switching at the time of supplying said current is superimposed on said optional shape of current pulse and is supplied to the machining gap.

摘要翻译： 在放电机的电源装置中，提供效率高，电流纹波小的电源，以实现电源尺寸和价格的降低。 此外，开关电源系统共同使用以产生可选的波形。 第一开关装置在与供给到加工间隙的电流脉冲的波形形状相对应的电流指令值信号的控制下，在可选择的周期内接通/断开，从而将可选形式的电流脉冲提供给 加工间隙和补偿在供给所述电流时由所述开关产生的电流纹波的电流分量叠加在所述可选形式的电流脉冲上，并被提供给加工间隙。

公开(公告)号：US09304507B2

公开(公告)日：2016-04-05

申请号：US13532876

申请日：2012-06-26

申请人： Junichi Tezuka ,  Hajime Ogawa

发明人： Junichi Tezuka ,  Hajime Ogawa

IPC分类号： G01P7/00 ,  G01C3/08 ,  G01M1/38 ,  G01B5/28 ,  G05B19/408 ,  G05B19/4069

CPC分类号： G05B19/408 ,  G05B19/4069 ,  G05B2219/35349

摘要： A tool path display apparatus (20) includes a tool coordinate value calculation unit (22) that calculates tool commanded coordinate values and tool actual coordinate values, based on commanded value time series data of position commands for a plurality of axes, detected value time series data of position detected values for the plurality of axes, and the structure of a machine tool, an acceleration calculation unit (23) that calculates accelerations of a tip point of a tool using the tool commanded coordinate values and the tool actual coordinate values, and a display format selection unit (24) that selects display formats of the accelerations of the tool commanded coordinate values and the tool actual coordinate values.

摘要翻译： 工具路径显示装置（20）包括：工具坐标值计算部（22），其基于多个轴的位置指令的指令值时间序列数据来计算刀具指令坐标值和刀具实际坐标值，检测值时间序列 用于多个轴的位置检测值的数据，以及机床的结构，加速度计算单元（23），其使用所述刀具指令坐标值和所述刀具实际坐标值来计算刀具的尖端的加速度，以及 显示格式选择单元（24），其选择工具指令坐标值的加速度和工具实际坐标值的显示格式。

公开(公告)号：US08988032B2

公开(公告)日：2015-03-24

申请号：US13564989

申请日：2012-08-02

申请人： Yasusuke Iwashita ,  Hajime Ogawa

发明人： Yasusuke Iwashita ,  Hajime Ogawa

IPC分类号： G05B19/18 ,  G05B19/4068

CPC分类号： G05B19/4068 ,  G05B2219/35349

摘要： A numerical controller capable of visually and accurately analyzing a change of the tool trajectory before and after changing a processing condition, whereby a parameter of a drive axis can be properly adjusted. The numerical controller comprises a numeric controlling part which controls each drive axis based on a predetermined position command; a position data obtaining part which obtains position data of each drive axis controlled by the numerical controlling part; a tool coordinate calculating part which calculates a coordinate of a tool center point based on position feedback or obtained position data of each drive axis and information of a mechanical structure of a machine tool; a tool trajectory storing part which stores the calculated coordinate of the tool center point as a feedback trajectory; and a displaying part which displays the stored feedback trajectory on a display.

摘要翻译： 一种数字控制器，其能够在改变处理条件之前和之后视觉上和精确地分析工具轨迹的变化，从而可以适当地调整驱动轴的参数。 数值控制器包括：数字控制部，其基于预定位置指令控制各驱动轴; 位置数据获取部，其获取由所述数值控制部控制的各驱动轴的位置数据; 工具坐标计算部，其基于位置反馈或所获得的各驱动轴的位置数据和机床的机械结构的信息来计算刀具中心点的坐标; 工具轨迹存储部，其将所计算的所述工具中心点的坐标存储为反馈轨迹; 以及在显示器上显示存储的反馈轨迹的显示部分。

公开(公告)号：USRE45199E1

公开(公告)日：2014-10-14

申请号：US13616573

申请日：2012-09-14

申请人： Shohei Michimoto ,  Taketo Heishi ,  Hajime Ogawa ,  Teruo Kawabata

发明人： Shohei Michimoto ,  Taketo Heishi ,  Hajime Ogawa ,  Teruo Kawabata

IPC分类号： G06F9/45

CPC分类号： G06F8/4452 ,  G06F8/433

摘要： A compiler apparatus, which can perform software pipelining optimization that has a considerable effect of reducing the number of execution cycles taken to complete a loop process, converts a source program into a machine program for a processor which is capable of parallel processing. The compiler apparatus is composed of: a parsing unit operable to parse the source program and then to convert the source program into an intermediate program which is described in an intermediate language; an optimization unit operable to optimize the intermediate program; and a conversion unit operable to convert the optimized intermediate program into the machine language program, wherein the optimization unit is operable to execute software pipelining, by inserting a transfer instruction, which is used for transferring data between operands, into a loop process included in the intermediate program so that a data dependence relation is changed.

摘要翻译： 可以执行软件流水线优化的编译器装置，其具有减少完成循环处理所执行的执行周期的数量的显着效果，将源程序转换为能够并行处理的处理器的机器程序。 编译装置由以下部分组成：解析单元，用于解析源程序，然后将源程序转换成以中间语言描述的中间程序; 可优化所述中间程序的优化单元; 以及转换单元，其可操作以将优化的中间程序转换成机器语言程序，其中所述优化单元可操作以通过将用于在操作数之间传送数据的传送指令插入到包括在所述机器语言程序中的循环处理中来执行软件流水线 中间程序，使数据依赖关系发生变化。

公开(公告)号：US08286145B2

公开(公告)日：2012-10-09

申请号：US12107450

申请日：2008-04-22

申请人： Teruo Kawabata ,  Masatsugu Daimon ,  Taketo Heishi ,  Hajime Ogawa

发明人： Teruo Kawabata ,  Masatsugu Daimon ,  Taketo Heishi ,  Hajime Ogawa

IPC分类号： G06F9/45

CPC分类号： G06F8/4441

摘要： A program re-writing method which re-writes an inputted program into a program for a processor for controlling whether or not a process is executed based on a yes or no execution flag, said program re-writing method including: inserting a comparison process into the inputted program, the comparison process comparing first address information, which is memory address information accessed by a first memory access process included in the inputted program, and second address information, which is address information of a memory accessed by a second memory access process included in the inputted program, and writing a comparison result into the yes or no execution flag; and inserting a yes or no execution flag-attached logic preservation process into the inputted program, the yes or no execution flag-attached logic preservation process being a process executed based on a value of the yes or no execution flag and preserving the same result as a result of the inputted program when executed.

摘要翻译： 一种程序重写方法，其将输入的程序重写到用于处理器的程序中，用于基于是或否执行标志来控制是否执行处理，所述程序重写方法包括：将比较处理插入到 所输入的程序，比较第一地址信息的比较处理，第一地址信息是由包括在输入的程序中的第一存储器访问处理访问的存储器地址信息和作为​​包括第二存储器访问处理访问的存储器的地址信息的第二地址信息 在输入的程序中，将比较结果写入是或否执行标志; 并且在输入的程序中插入“是”或“否”执行标志附加的逻辑保存处理，“是”或“否”执行标志附加的逻辑保存处理是基于“是”或“否”执行标志的值执行的处理，并且保持与 执行时输入程序的结果。

公开(公告)号：US07856629B2

公开(公告)日：2010-12-21

申请号：US11420059

申请日：2006-05-24

申请人： Shohei Michimoto ,  Taketo Heishi ,  Hajime Ogawa ,  Teruo Kawabata

发明人： Shohei Michimoto ,  Taketo Heishi ,  Hajime Ogawa ,  Teruo Kawabata

IPC分类号： G06F9/45

CPC分类号： G06F8/4452 ,  G06F8/433

摘要： A compiler apparatus, which can perform software pipelining optimization that has a considerable effect of reducing the number of execution cycles taken to complete a loop process, converts a source program into a machine program for a processor which is capable of parallel processing. The compiler apparatus is composed of: a parsing unit operable to parse the source program and then to convert the source program into an intermediate program which is described in an intermediate language; an optimization unit operable to optimize the intermediate program; and a conversion unit operable to convert the optimized intermediate program into the machine language program, wherein the optimization unit is operable to execute software pipelining, by inserting a transfer instruction, which is used for transferring data between operands, into a loop process included in the intermediate program so that a data dependence relation is changed.

摘要翻译： 可以执行软件流水线优化的编译器装置，其具有减少完成循环处理所执行的执行周期的数量的显着效果，将源程序转换为能够并行处理的处理器的机器程序。 编译装置由以下部分组成：解析单元，用于解析源程序，然后将源程序转换成以中间语言描述的中间程序; 可优化所述中间程序的优化单元; 以及转换单元，其可操作以将优化的中间程序转换成机器语言程序，其中所述优化单元可操作以通过将用于在操作数之间传送数据的传送指令插入到包括在所述机器语言程序中的循环处理中来执行软件流水线 中间程序，使数据依赖关系发生变化。

公开(公告)号：US07185324B2

公开(公告)日：2007-02-27

申请号：US10631960

申请日：2003-08-01

申请人： Shohei Michimoto ,  Hajime Ogawa ,  Toshiyuki Sakata ,  Taketo Heishi ,  Shuichi Takayama

发明人： Shohei Michimoto ,  Hajime Ogawa ,  Toshiyuki Sakata ,  Taketo Heishi ,  Shuichi Takayama

IPC分类号： G06F9/45 ,  G06F12/00 ,  G06F12/02

CPC分类号： G06F9/5016 ,  G06F8/443 ,  G06F9/44557

摘要： Disclosed is a compiler apparatus for generating an instruction code composed of instruction sets each including an instruction that designates an m-bit immediate value indicating a location of a data item in a memory area. The compiler apparatus sequentially selects, based on one data attribute, a data item from a group X composed of a plurality of data items; and judges, each time a data item is selected, whether the selected data item is allocatable to an n-byte memory area (n≦2m). When the judgment is negative, the compiler apparatus specifies, based on a different data attribute, a data item out of all the selected data items and excludes the specified data item from the group X, and repeats the selection until all the data items remaining in the group X after excluding specified data items are judged to be allocatable to the memory area.

摘要翻译： 公开了一种编译装置，用于生成由指令集构成的指令代码，每个指令集包括指定指示存储区中的数据项的位置的m位立即值的指令。 编译装置根据一个数据属性从由多个数据项组成的组X中依次选择数据项; 并且每当选择数据项时，判断所选择的数据项是否可分配给n字节存储区（n <= 2 ^{m）。 当判断为否定时，编译装置根据不同的数据属性指定所有选择的数据项中的数据项，并从组X中排除指定的数据项，并重复选择，直到剩余的所有数据项 在排除指定数据项之后的组X被判断为可分配给存储区。}

公开(公告)号：US06993756B2

公开(公告)日：2006-01-31

申请号：US09798490

申请日：2001-03-02

申请人： Hajime Ogawa ,  Shuichi Takayama

发明人： Hajime Ogawa ,  Shuichi Takayama

IPC分类号： G06F9/45

CPC分类号： G06F8/452 ,  G06F8/4452

摘要： An optimization apparatus is capable of improving the execution efficiency of a loop that includes a loop carry dependency between consecutive iterations of the loop. For example, a value resulting from one iteration is used in an immediately following iteration. When the arithmetic expression “a[i+1]=a[i]*3+2;” is included in a loop body, and a value resulting from the arithmetic expression “a[i+1]=a[i]*3+2;” in one iteration is used in a following iteration, execution delays occur in pipeline processing of the loop. Here, the arithmetic expression “a[i+1]=a[i]*3+2;” is transformed into the arithmetic expression “a[i+4]=a[i]*81+80;” to expand the dependency distance. By doing so, the execution delays can be decreased.

摘要翻译： 优化装置能够提高循环的执行效率，该循环在循环的连续迭代之间包括循环进位依赖性。 例如，由一次迭代产生的值在紧随其后的迭代中使用。 当算术表达式“a [i + 1] = a [i] * 3 + 2;” 被包含在循环体中，并且由算术表达式“a [i + 1] = a [i] * 3 + 2]得到的值; 在一次迭代中，在下一次迭代中使用，在循环的流水线处理中出现执行延迟。 这里，算术表达式“a [i + 1] = a [i] * 3 + 2;” 被转换成算术表达式“a [i + 4] = a [i] * 81 + 80;” 扩大依赖距离。 通过这样做，可以减少执行延迟。

公开(公告)号：US06880150B1

公开(公告)日：2005-04-12

申请号：US09301284

申请日：1999-04-28

申请人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

发明人： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/44

CPC分类号： G06F9/3802 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3853

摘要： When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

摘要翻译： 当指令解码器409a〜409c解码分支指令时，分支指令中包含的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。 下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。 上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。