公开(公告)号：US20070075952A1

公开(公告)日：2007-04-05

申请号：US11526059

申请日：2006-09-25

申请人： Yoshihisa Hamahashi ,  Tomoya Ishikawa ,  Tetsuo Asada ,  Yoshito Date ,  Yasuyuki Doi

发明人： Yoshihisa Hamahashi ,  Tomoya Ishikawa ,  Tetsuo Asada ,  Yoshito Date ,  Yasuyuki Doi

IPC分类号： G09G3/36

CPC分类号： G09G3/2011 ,  G09G2310/027 ,  G09G2320/0233

摘要： Each of first and second decoders outputs two voltages each having a voltage value equal to any one of a plurality of gray-level voltages according to gray-level data as two selection voltages or outputs any two of the plurality of gray-level voltages according to gray-level data as the two selection voltages. A connection switching circuit associates one of the first and second decoders with a first differential amplifier and the other decoder with a second differential amplifier. An output switching circuit associates one of the first and second differential amplifiers with a first output node and the other differential amplifier with a second output node. Each of the first and second differential amplifiers synthesizes selection voltages output from the decoder associated with the differential amplifier to generate a driving voltage and outputs the generated driving voltage to the output node associated with the differential amplifier.

摘要翻译： 第一解码器和第二解码器中的每一个根据作为两个选择电压的灰度级数据输出各自具有等于多个灰度级电压中的任何一个的电压值的两个电压，或者输出多个灰度级电压中的任何两个根据 灰度级数据作为两个选择电压。 连接切换电路将第一和第二解码器中的一个与第一差分放大器和另一个解码器与第二差分放大器相关联。 输出切换电路将第一和第二差分放大器之一与第一输出节点和另一个具有第二输出节点的差分放大器相关联。 第一和第二差分放大器中的每一个合成从与差分放大器相关联的解码器输出的选择电压以产生驱动电压，并将产生的驱动电压输出到与差分放大器相关联的输出节点。

公开(公告)号：US20070146231A1

公开(公告)日：2007-06-28

申请号：US11641875

申请日：2006-12-20

申请人： Yoshihisa Hamahashi ,  Yasuyuki Doi ,  Tooru Suyama ,  Makoto Hattori ,  Tomoya Ishikawa

发明人： Yoshihisa Hamahashi ,  Yasuyuki Doi ,  Tooru Suyama ,  Makoto Hattori ,  Tomoya Ishikawa

IPC分类号： G09G5/00

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2320/0223 ,  G09G2330/021 ,  G09G2330/028 ,  G09G2370/08

摘要： A receiving circuit receives one or plural first signals involving display from the outside through an input unit. A first transmitting circuit transmits one or plural second signals relevant to the first signal from the first output unit. A second transmitting circuit transmits the second signal from the second output unit.

摘要翻译： 接收电路通过输入单元从外部接收涉及显示的一个或多个第一信号。 第一发送电路从第一输出单元发送与第一信号相关的一个或多个第二信号。 第二发送电路从第二输出单元发送第二信号。

公开(公告)号：US20050174145A1

公开(公告)日：2005-08-11

申请号：US10513965

申请日：2003-08-27

申请人： Shiro Dosho ,  Yusuke Tokunaga ,  Yasuyuki Doi ,  Hirofumi Nakagawa ,  Yoshito Date ,  Tetsuro Ohmori ,  Kaori Nishikawa

发明人： Shiro Dosho ,  Yusuke Tokunaga ,  Yasuyuki Doi ,  Hirofumi Nakagawa ,  Yoshito Date ,  Tetsuro Ohmori ,  Kaori Nishikawa

IPC分类号： G09G3/36 ,  H04L25/02 ,  H04L25/49 ,  H03K19/094

CPC分类号： G09G3/3685 ,  G09G2310/027 ,  G09G2330/06 ,  H04L25/0272 ,  H04L25/4902

摘要： In the process of transferring a clock signal and a plurality of data signals which are in synchronization with the clock signal, a driving pulse width of a driver switch is feedback-controlled by a clock transmission system (12), whereby the clock signal is transmitted at a small amplitude. A control signal having the pulse width is used for controlling the driver switch in each data transmission system (13), whereby transfer of each data signal at a small amplitude is realized at the same time. Further, in a clock reception system (10), the control signal having the pulse width is used in delay control of a clock delay circuit, whereby an optimum latch timing of received data in each data reception system (11) is realized.

摘要翻译： 在传送与时钟信号同步的时钟信号和多个数据信号的过程中，驱动器开关的驱动脉冲宽度被时钟传输系统（12）反馈控制，从而传输时钟信号 在一个小幅度。 具有脉冲宽度的控制信号用于控制每个数据传输系统（13）中的驱动器开关，从而同时实现以小幅度传送每个数据信号。 此外，在时钟接收系统（10）中，具有脉冲宽度的控制信号用于时钟延迟电路的延迟控制，从而实现每个数据接收系统（11）中的接收数据的最佳锁存定时。

公开(公告)号：US07119802B2

公开(公告)日：2006-10-10

申请号：US10350421

申请日：2003-01-24

申请人： Tooru Suyama ,  Tsutomu Sakakibara ,  Tomokazu Kojima ,  Tetsuro Ohmori ,  Yoshito Date ,  Yasuyuki Doi ,  Masahiro Akabori ,  Kenji Miyake ,  Miki Fujino ,  Takahito Kushima ,  Tsukasa Kawahara ,  Kazuhiko Nagaoka ,  Shinji Miyamoto ,  Yoshiyuki Konishi

发明人： Tooru Suyama ,  Tsutomu Sakakibara ,  Tomokazu Kojima ,  Tetsuro Ohmori ,  Yoshito Date ,  Yasuyuki Doi ,  Masahiro Akabori ,  Kenji Miyake ,  Miki Fujino ,  Takahito Kushima ,  Tsukasa Kawahara ,  Kazuhiko Nagaoka ,  Shinji Miyamoto ,  Yoshiyuki Konishi

IPC分类号： G09G5/00

CPC分类号： H03F3/45941 ,  G09G3/3655 ,  G09G2330/022 ,  H03F3/45946 ,  H03F2203/45622 ,  H03F2203/45732

摘要： A compact-size driving voltage controller is provided which can be driven with low power. The compact-size driving voltage controller which can be driven with low power includes a High output operational amplifier and a Low output operational amplifier for supplying driving voltages VcomH, VcomL to a load such as a liquid crystal display panel, an output switch for alternating between the outputs of the operational amplifiers, a Low voltage setting operational amplifier for generating a set voltage to be supplied to the non-inverted input terminal of the Low output operational amplifier, a set voltage generator including a current mirror circuit and a clamping circuit, a bias current controller for controlling the bias current flowing in each operational amplifier with a predetermined timing, and a timing controller for controlling the changeover timing of the output switch.

摘要翻译： 提供了可以以低功率驱动的紧凑型驱动电压控制器。 可以以低功率驱动的紧凑型驱动电压控制器包括高输出运算放大器和用于向诸如液晶显示面板的负载提供驱动电压VcomH，VcomL的低输出运算放大器，用于在 运算放大器的输出，用于产生要提供给低输出运算放大器的非反相输入端的设定电压的低电压设置运算放大器，包括电流镜电路和钳位电路的设定电压发生器， 偏置电流控制器，用于以预定定时控制在每个运算放大器中流动的偏置电流;以及定时控制器，用于控制输出开关的转换定时。

公开(公告)号：US07009426B2

公开(公告)日：2006-03-07

申请号：US10513965

申请日：2003-08-27

申请人： Shiro Dosho ,  Yusuke Tokunaga ,  Yasuyuki Doi ,  Hirofumi Nakagawa ,  Yoshito Date ,  Tetsuro Ohmori ,  Kaori Nishikawa

发明人： Shiro Dosho ,  Yusuke Tokunaga ,  Yasuyuki Doi ,  Hirofumi Nakagawa ,  Yoshito Date ,  Tetsuro Ohmori ,  Kaori Nishikawa

IPC分类号： H03K19/00

CPC分类号： G09G3/3685 ,  G09G2310/027 ,  G09G2330/06 ,  H04L25/0272 ,  H04L25/4902

摘要： In the process of transferring a clock signal and a plurality of data signals which are in synchronization with the clock signal, a driving pulse width of a driver switch is feedback-controlled by a clock transmission system (12), whereby the clock signal is transmitted at a small amplitude. A control signal having the pulse width is used for controlling the driver switch in each data transmission system (13), whereby transfer of each data signal at a small amplitude is realized at the same time. Further, in a clock reception system (10), the control signal having the pulse width is used in delay control of a clock delay circuit, whereby an optimum latch timing of received data in each data reception system (11) is realized.

摘要翻译： 在传送与时钟信号同步的时钟信号和多个数据信号的过程中，驱动器开关的驱动脉冲宽度由时钟传输系统（12）进行反馈控制，从而传输时钟信号 在一个小幅度。 具有脉冲宽度的控制信号用于控制每个数据传输系统（13）中的驱动器开关，从而同时实现以小幅度传送每个数据信号。 此外，在时钟接收系统（10）中，具有脉冲宽度的控制信号用于时钟延迟电路的延迟控制，从而实现每个数据接收系统（11）中的接收数据的最佳锁存定时。

公开(公告)号：US07388405B2

公开(公告)日：2008-06-17

申请号：US11513239

申请日：2006-08-31

申请人： Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Yasuyuki Doi ,  Makoto Hattori

发明人： Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Yasuyuki Doi ,  Makoto Hattori

IPC分类号： H03K19/094 ,  H03K19/0175 ,  H03B1/00

CPC分类号： H03K19/018571 ,  H03F1/0261 ,  H03F3/505 ,  H03F2200/18 ,  H04L25/028

摘要： A time required for an output voltage of a source follower to rise from Low to a predetermined voltage depends on a bias voltage. Therefore, by setting a converged voltage of an output voltage to be high by increasing the bias voltage, the time required to rise up to the predetermined voltage can be reduced. Therefore, a first source follower which is biased so that the converged value of the output voltage becomes a predetermined Hi voltage when an input data signal goes from Low to Hi, and a second source follower which is biased so as to become the Hi voltage after a period of one clock when an input data signal goes from Low to Hi, are used. The two source followers are operated with appropriate timing.

摘要翻译： 源极跟随器的输出电压从低电平上升到预定电压所需的时间取决于偏置电压。 因此，通过增加偏置电压来设定输出电压的收敛电压为高，可以降低上升到预定电压所需的时间。 因此，当输入数据信号从低电平变为高电平时，被偏压使得输出电压的会聚值变为预定的Hi电压的第一源极跟随器，以及被偏置以便成为Hi电压之后的第二源极跟随器 使用输入数据信号从低电平变为高电平时的一个时钟周期。 两个来源追随者在适当的时机运行。

公开(公告)号：US20060176091A1

公开(公告)日：2006-08-10

申请号：US11289753

申请日：2005-11-30

申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata ,  Hideki Yoshii ,  Yasuyuki Doi ,  Makoto Hattori

发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata ,  Hideki Yoshii ,  Yasuyuki Doi ,  Makoto Hattori

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/07 ,  H03L7/0891 ,  H03L7/0895

摘要： A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.

摘要翻译： 延迟元件产生延迟的时钟信号，该时钟信号以基于参考时钟信号的上升（或下降）的延迟从基于环路滤波器的输出确定的延迟量转变。 信号产生电路产生根据参考时钟信号的上升和下降以及延迟的时钟信号的转变而互补地变化的两个信号。 电荷泵电路根据这两个信号执行环路滤波器，在从参考时钟信号的上升（或下降）延迟到延迟的时钟信号的转换的延迟期间进行推（或拉） （或推动）操作在从延迟的时钟信号的转变延伸到参考时钟信号的下降（或上升）的间隔期间。

公开(公告)号：US06982706B1

公开(公告)日：2006-01-03

申请号：US10019437

申请日：2000-08-31

申请人： Yasuyuki Doi ,  Tetsuro Oomori ,  Kazuyoshi Nishi

发明人： Yasuyuki Doi ,  Tetsuro Oomori ,  Kazuyoshi Nishi

IPC分类号： G09G5/00

CPC分类号： G09G3/2011 ,  G09G3/3614 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2310/027

摘要： A source driver 4A arranged on a liquid crystal panel includes therein in-chip reference voltage wires 17 extending from one end to the other end of an LSI chip. The source driver 4A includes therein: branch reference voltage wires 17a branching off from in-chip reference voltage wires 17; reference voltage production buffers 31; a control circuit 30 for controlling the reference voltage production buffers 31; a reference voltage production resistor section 32 for subdividing the reference voltage into values of n steps; voltage level selection circuits 34 each for selecting one of the subdivided voltages; and output buffers 35. Since the reference voltages are supplied to each source driver 4 via wiring for connecting the in-chip reference voltage wires 17 in series with one another, the wiring structure for supplying the reference voltages can be simplified.

摘要翻译： 布置在液晶面板上的源极驱动器4A包括从LSI芯片的一端延伸到另一端的片上参考电压电线17。 源极驱动器4A包括：从芯片上参考电压线17分支的分支参考电压线17a; 参考电压产生缓冲器31; 用于控制参考电压产生缓冲器31的控制电路30; 参考电压产生电阻器部分32，用于将参考电压分为n个步骤的值; 每个电压电平选择电路34用于选择一个分割电压; 和输出缓冲器35。 由于通过用于将片上参考电压线17串联连接的布线将参考电压提供给每个源极驱动器4，因此可以简化用于提供参考电压的布线结构。

公开(公告)号：US07479941B2

公开(公告)日：2009-01-20

申请号：US11175137

申请日：2005-07-07

申请人： Kazuya Matsumoto ,  Yasuyuki Doi

发明人： Kazuya Matsumoto ,  Yasuyuki Doi

IPC分类号： G09G3/36

CPC分类号： G09G5/006

摘要： In order to correctly hold a low-amplitude input signal even when the operating speed of a display element drive apparatus is high, a differential signal including a pair of CLKP1 and CLKN1 is input to a first comparator and a second comparator in a manner that provides opposite phases between respective output voltage signals. An output of the first comparator is frequency-divided by the first frequency dividing flip-flop, while an output of the second comparator is frequency-divided by the second frequency dividing flip-flop. A first data holding flip-flop holds an input data signal in synchronization with a signal output by a first frequency dividing flip-flop, while a second data holding flip-flop holds an input data signal in synchronization with a signal output by a second frequency dividing flip-flop.

摘要翻译： 为了正确地保持低振幅输入信号，即使在显示元件驱动装置的操作速度高的情况下，包括一对CLKP1和CLKN1的差分信号以提供的方式输入到第一比较器和第二比较器 各个输出电压信号之间的相位相位。 第一比较器的输出被第一分频触发器分频，而第二比较器的输出被第二分频触发器分压。 第一数据保持触发器保持与由第一分频触发器输出的信号同步的输入数据信号，而第二数据保持触发器与输出的第二频率的信号同步地保持输入数据信号 分频触发器。

公开(公告)号：US06392485B1

公开(公告)日：2002-05-21

申请号：US09663388

申请日：2000-09-15

申请人： Yasuyuki Doi ,  Tetsuro Oomori

发明人： Yasuyuki Doi ,  Tetsuro Oomori

IPC分类号： H03F345

CPC分类号： H03F3/45219 ,  G09G3/3688 ,  H03F3/4565 ,  H03F3/68 ,  H03F2203/45431 ,  H03F2203/45448 ,  H03F2203/45451

摘要： It is an object of the present invention to provide a high slew rate differential amplifier circuit that can reduce current consumption while maintaining stability. A P-type MOS sub-current source (6) having a current source circuit including a transistor (M18) having a gate voltage of a P-type MOS output transistor (M15) input to a gate thereof and a constant current source transistor (M17) connected in series with the transistor (M18), the current source circuit being connected in parallel with a constant current source transistor (M1) of a P-type MOS differential input section (1) is combined with an N-type MOS sub-current source (7) including a current source circuit including a transistor (M19) having a gate voltage of an N-type MOS output transistor (M16) input to a gate thereof and a constant current source transistor (M20) connected in series with the transistor (M19), the current source circuit being connected in parallel with a constant current source transistor (M6) of an N-type MOS differential input section (2). To increase a current through the differential input section when a high slew rate is required, the current source circuit including the transistor having the gate voltage of the output transistor input to the gate thereof and the constant current source transistor connected in series with the first transistor is used as a sub-current source for a differential circuit, in order to reduce a steady-state current.

摘要翻译： 本发明的目的是提供一种可以在保持稳定性的同时降低电流消耗的高压摆率差分放大器电路。 一种具有电流源电路的P型MOS子电流源（6），包括具有输入到其栅极的P型MOS输出晶体管（M15）的栅极电压的晶体管（M18）和恒流源晶体管 M17），与P型MOS差分输入部（1）的恒流源晶体管（M1）并联连接的电流源电路与N型MOS子晶体管（M18）组合， 电流源（7），包括电流源电路，其包括具有输入到其栅极的N型MOS输出晶体管（M16）的栅极电压的晶体管（M19）和与栅极串联连接的恒流源晶体管（M20） 所述晶体管（M19），所述电流源电路与N型MOS差分输入部（2）的恒流源晶体管（M6）并联连接。 为了在需要高压摆率时增加通过差分输入部分的电流，电流源电路包括输入到其栅极的输出晶体管的栅极电压的晶体管和与第一晶体管串联连接的恒流源晶体管 被用作差分电路的子电流源，以便降低稳态电流。