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公开(公告)号：US07812398B2
公开(公告)日：2010-10-12
申请号：US12400324
申请日：2009-03-09
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/045 , H01L29/7846 , H01L29/785
摘要： A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.
摘要翻译： 提供了一种半导体器件及其制造方法，其中通过使用现有的硅工艺容易地形成的方案，增加了pMOSFET的驱动电流。 在（100）硅衬底上形成具有<100>方向的沟道的pMOSFET。 通过STI在垂直于通道的方向上施加压应力。
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公开(公告)号：US20070284582A1
公开(公告)日：2007-12-13
申请号：US11746230
申请日：2007-05-09
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/045 , H01L29/7846 , H01L29/785
摘要： A semiconductor device and manufacturing method of the same is provided in which the driving current of a PMOSFET is increased, through a scheme formed easily using an existing silicon process. A PMOSFET is formed with a channel in a direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.
摘要翻译： 提供了一种半导体器件及其制造方法，其中通过使用现有的硅工艺容易地形成的方案，PMOSFET的驱动电流增加。 在（100）硅衬底上形成具有沿<100>方向的沟道的PMOSFET。 通过STI在垂直于通道的方向上施加压应力。
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公开(公告)号：US07531853B2
公开(公告)日：2009-05-12
申请号：US11746230
申请日：2007-05-09
IPC分类号： H01L29/80 , H01L31/112 , H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/045 , H01L29/7846 , H01L29/785
摘要： A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.
摘要翻译： 提供了一种半导体器件及其制造方法，其中通过使用现有的硅工艺容易地形成的方案，增加了pMOSFET的驱动电流。 在（100）硅衬底上形成具有<100>方向的沟道的pMOSFET。 通过STI在垂直于通道的方向上施加压应力。
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公开(公告)号：US20060081836A1
公开(公告)日：2006-04-20
申请号：US11249681
申请日：2005-10-14
IPC分类号： H01L31/109
CPC分类号： H01L21/823425 , H01L21/823412 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/41758 , H01L29/4238 , H01L29/66659 , H01L29/7835
摘要： In a field effect semiconductor device for high frequency power amplification, it is difficult to achieve size reduction and increased efficiency simultaneously while ensuring voltage withstanding. A further improvement in efficiency is attained by using a strained Si channel for LDMOS at an output stage for high frequency power amplification. Further, the efficiency is improved as much as possible while decreasing a leak current, by optimizing the film thickness of the strained Si layer having a channel region, inactivation of defects and a field plate structure.
摘要翻译： 在用于高频功率放大的场效半导体器件中，难以在确保耐压的同时实现尺寸减小和提高效率。 通过在高频功率放大的输出级使用用于LDMOS的应变Si通道来实现效率的进一步提高。 此外，通过优化具有通道区域的应变Si层的膜厚度，缺陷的失活和场板结构，尽可能地提高效率同时减小漏电流。
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公开(公告)号：US07890898B2
公开(公告)日：2011-02-15
申请号：US12024107
申请日：2008-01-31
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Capacity-gate voltage characteristics of a field-effect transistor having plural gates are measured against a voltage change in each one of the gates for an inverted MOSFET and for an accumulated MOSFET, respectively. These measurements together with numerical simulations provided from a model for quantum effects are used to determine flat band voltages between the plural gates and a channel. Next, an effective normal electric field is calculated as a vector line integral by using a set of flat band voltages for the measured capacity as a lower integration limit. Lastly, mobility depending on the effective normal electric field is calculated from current-gate voltage characteristic measurements and capacity measurements in a source-drain path, and the calculated mobility is substituted into an equation for a current-voltage curve between source and drain.
摘要翻译： 针对反向MOSFET的栅极和积累的MOSFET中的每一个的电压变化分别测量具有多个栅极的场效应晶体管的容量栅极电压特性。 这些测量结果与从量子效应模型提供的数值模拟一起用于确定多个门和通道之间的平带电压。 接下来，通过使用一组用于测量容量的平带电压作为下积分极限，计算有效正常电场作为矢量线积分。 最后，根据源极 - 漏极路径中的电流 - 栅极电压特性测量和电容测量值计算出有效正常电场的迁移率，并将计算的迁移率代入源极和漏极之间的电流 - 电压曲线的方程式。
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公开(公告)号：US20090132974A1
公开(公告)日：2009-05-21
申请号：US12024107
申请日：2008-01-31
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Capacity-gate voltage characteristics of a field-effect transistor having plural gates are measured against a voltage change in each one of the gates for an inverted MOSFET and for an accumulated MOSFET, respectively. These measurements together with numerical simulations provided from a model for quantum effects are used to determine flat band voltages between the plural gates and a channel. Next, an effective normal electric field is calculated as a vector line integral by using a set of flat band voltages for the measured capacity as a lower integration limit. Lastly, mobility depending on the effective normal electric field is calculated from current-gate voltage characteristic measurements and capacity measurements in a source-drain path, and the calculated mobility is substituted into an equation for a current-voltage curve between source and drain.
摘要翻译： 针对反向MOSFET的栅极和积累的MOSFET中的每一个的电压变化分别测量具有多个栅极的场效应晶体管的容量栅极电压特性。 这些测量结果与从量子效应模型提供的数值模拟一起用于确定多个门和通道之间的平带电压。 接下来，通过使用一组用于测量容量的平带电压作为下积分极限，计算有效正常电场作为矢量线积分。 最后，根据源极 - 漏极路径中的电流 - 栅极电压特性测量和电容测量值计算出有效正常电场的迁移率，并将计算的迁移率代入源极和漏极之间的电流 - 电压曲线的方程式。
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公开(公告)号：US20080258218A1
公开(公告)日：2008-10-23
申请号：US12105226
申请日：2008-04-17
IPC分类号： H01L27/01
CPC分类号： H01L29/045 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/7834
摘要： A MIS transistor having an inclined stacked source/drain structure increased in speed is provided. The MIS transistor comprises: a gate electrode formed on a substrate; a first sidewall insulating film formed on the substrate and along a sidewall of the gate electrode; source/drain semiconductor regions formed on a main surface of the substrate and respectively having one edge positioned under the sidewall of the gate electrode; a first stacked layer formed on the source/drain semiconductor regions and in contact with the first sidewall insulating film; a second sidewall insulating film formed on the stacked layer and in contact with the first sidewall insulating film; and a second stacked layer formed on the first stacked layer and in contact with the second sidewall insulating layer.
摘要翻译： 提供了具有倾斜堆叠的源极/漏极结构的MIS晶体管，其速度提高。 MIS晶体管包括：形成在衬底上的栅电极; 形成在所述基板上并沿着所述栅电极的侧壁的第一侧壁绝缘膜; 源极/漏极半导体区域，形成在基板的主表面上，并且分别具有位于栅电极的侧壁下方的一个边缘; 形成在所述源极/漏极半导体区域上并与所述第一侧壁绝缘膜接触的第一堆叠层; 形成在所述层叠层上并与所述第一侧壁绝缘膜接触的第二侧壁绝缘膜; 以及形成在第一堆叠层上并与第二侧壁绝缘层接触的第二堆叠层。
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公开(公告)号：US08183635B2
公开(公告)日：2012-05-22
申请号：US12756451
申请日：2010-04-08
申请人： Nobuyuki Sugii , Ryuta Tsuchiya , Shinichiro Kimura , Takashi Ishigaki , Yusuke Morita , Hiroyuki Yoshimoto
发明人： Nobuyuki Sugii , Ryuta Tsuchiya , Shinichiro Kimura , Takashi Ishigaki , Yusuke Morita , Hiroyuki Yoshimoto
IPC分类号： H01L21/00
CPC分类号： H01L27/1203 , H01L21/76283
摘要： A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.
摘要翻译： 通过改善在SOI衬底的浅沟槽和SOI层的边界部分的形状来实现低功耗的半导体器件的技术。 硅衬底的主表面和沿着SOI层的侧表面延伸的线交叉的位置（SOI边缘）比浅沟槽隔离更远离位于（STI边缘）的位置（STI边缘），在该位置处 沿着浅沟槽的侧壁延伸并且沿着硅衬底的主表面延伸的线交叉，并且在STI边缘处的硅衬底的拐角具有弯曲表面。
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公开(公告)号：US20100258871A1
公开(公告)日：2010-10-14
申请号：US12759559
申请日：2010-04-13
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： Characteristics of a semiconductor device having a FINFET are improved. The FINFET has: a channel layer arranged in an arch shape on a semiconductor substrate and formed of monocrystalline silicon; a front gate electrode formed on a part of an outside of the channel layer through a front gate insulating film; and a back gate electrode formed so as to be buried inside the channel layer through a back gate insulating film. The back gate electrode arranged inside the arch shape is arranged so as to pass through the front gate electrode.
摘要翻译： 具有FINFET的半导体器件的特性得到改善。 FINFET具有：在半导体衬底上以拱形形式布置并由单晶硅形成的沟道层; 前栅电极，其通过前栅极绝缘膜形成在沟道层的外部的一部分上; 以及形成为通过背栅绝缘膜埋设在沟道层内的背栅电极。 布置在拱形内侧的背栅极布置成穿过前栅电极。
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10.发明授权公开(公告)号：US08143668B2
公开(公告)日：2012-03-27
申请号：US12481551
申请日：2009-06-09
IPC分类号： H01L29/78
CPC分类号： H01L21/823814 , H01L21/823828 , H01L21/823864
摘要： Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.
摘要翻译： 提高了具有MIS晶体管的半导体器件的性能。 半导体器件包括：一对源极/漏极区域，每个源极/漏极区域通过在硅衬底的主表面上层叠半导体层而形成; 覆盖源极/漏极区域的每个侧壁的侧壁绝缘膜; 栅电极，被布置成在平面内被所述侧壁绝缘膜夹持的位置处在所述硅衬底的主表面上插入栅极绝缘膜; 以及延伸区域，其形成为从栅极电极下方和横向的部分延伸到每个源极/漏极区域的下方和侧面的部分，其中侧壁绝缘膜的侧壁与栅极绝缘膜和栅极电极相邻 具有向前锥形的倾斜。
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