公开(公告)号：US5500379A

公开(公告)日：1996-03-19

申请号：US265104

申请日：1994-06-24

申请人： Yoshinori Odake ,  Teruhito Ohnishi ,  Minoru Fujii

发明人： Yoshinori Odake ,  Teruhito Ohnishi ,  Minoru Fujii

IPC分类号： H01L21/8238 ,  H01L21/265

CPC分类号： H01L21/823807 ,  Y10S148/082

摘要： In a CMOS semiconductor device, low-dose ion implant of p-type impurity and n-type impurity is successively conducted to both n-MOSFET and p-MOSFET after formation of gate electrodes. Thereafter, when source/drain regions are formed at each MOSFET, p.sup.- regions function as local punch through stoppers in the n-MOSFET and n.sup.- regions function as the local punch through stoppers in the p-MOSFET. At this time, respective doses of n-type and p-type impurities are adjusted so that lowerings of threshold values of the channel regions are almost equal to each other. Thus, short channel effect is prevented, while reducing the step of forming two resist masks. With side walls, the CMOS semiconductor device with less short channel effect and high durability to hot carrier is manufactured without increase in the step of forming the resist masks.

摘要翻译： 在CMOS半导体器件中，p型杂质和n型杂质的低剂量离子注入在形成栅电极之后依次传导到n-MOSFET和p-MOSFET两者。 此后，当在每个MOSFET处形成源极/漏极区域时，p-区域用作n-MOSFET中的阻挡器的局部冲击，并且n-区域用作p-MOSFET中的局部冲击穿过止动器。 此时，调整各种剂量的n型和p型杂质，使得沟道区的阈值的降低几乎相等。 因此，防止短沟道效应，同时减少形成两个抗蚀剂掩模的步骤。 利用侧壁，在不增加形成抗蚀剂掩模的步骤的情况下，制造具有较短沟道效应和对热载体的高耐久性的CMOS半导体器件。

公开(公告)号：US6030869A

公开(公告)日：2000-02-29

申请号：US158985

申请日：1998-09-23

申请人： Yoshinori Odake ,  Takashi Maejima ,  Hidenori Tanaka ,  Mitsuyoshi Andou ,  Toshimoto Kubota

发明人： Yoshinori Odake ,  Takashi Maejima ,  Hidenori Tanaka ,  Mitsuyoshi Andou ,  Toshimoto Kubota

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L27/115 ,  H01L29/7885 ,  H01L21/26586

摘要： A method for fabricating a nonvolatile semiconductor memory device having a stacked gate portion, including a tunnel insulating film, a floating gate electrode, a capacitive insulating film and a control gate electrode, formed over a p-type Si substrate. In the p-type Si substrate, n.sup.++ source/drain layers and n.sup.+ source/drain layers, each layer containing arsenic, are formed. In the drain region, an n.sup.- drain layer, containing phosphorus and overlapping with an entire edge of the stacked gate portion in the gate width direction, and a p layer surrounding the bottoms of the n.sup.+ and the n.sup.- drain layers are provided. In such a structure, an electric field applied between the floating gate electrode and the drain is weakened and the drain-disturb characteristics are improved during writing.

摘要翻译： 一种在p型Si衬底上形成的具有堆叠栅极部分的非易失性半导体存储器件的方法，其包括隧道绝缘膜，浮栅电极，电容绝缘膜和控制栅电极。 在p型Si衬底中，形成n ++源极/漏极层和n +源极/漏极层，每个含有砷的层都形成。 在漏极区域中，设置有包含磷并且在栅极宽度方向上与堆叠栅极部分的整个边缘重叠的n沟道漏极层和围绕n +和n-drain层的底部的p层。 在这种结构中，在浮置栅电极和漏极之间施加的电场减弱，并且在写入期间漏极干扰特性得到改善。

公开(公告)号：US20060039175A1

公开(公告)日：2006-02-23

申请号：US11195652

申请日：2005-08-03

申请人： Yoshinori Odake

发明人： Yoshinori Odake

IPC分类号： G11C11/22

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11536

摘要： A first conductive film for forming a plurality of word lines is formed in a memory cell array formation region of a semiconductor substrate for a nonvolatile semiconductor memory device, and a second conductive film is formed in a semiconductor device formation region of the semiconductor substrate. Next, openings are formed in the first conductive film by a first dry etching process such that the word lines in the memory cell array formation region are located apart from one another. Thereafter, sidewall insulating films for the word lines are formed in the openings. Next, parts of the sidewall insulating films located adjacent to the ends of the word lines are removed by wet etching. Next, a part of the first conductive film located around a word line formation region is removed by a second dry etching process. The openings are formed in the first conductive film such that a part of the first conductive film remaining after the formation of the openings is continuous with the second conductive film, which is formed on an active region of the semiconductor substrate located outside the memory cell array formation region so as to be electrically connected to the active region.

摘要翻译： 用于形成多个字线的第一导电膜形成在用于非易失性半导体存储器件的半导体衬底的存储单元阵列形成区域中，并且在半导体衬底的半导体器件形成区域中形成第二导电膜。 接下来，通过第一干蚀刻工艺在第一导电膜中形成开口，使得存储单元阵列形成区域中的字线彼此分开。 此后，在开口中形成用于字线的侧壁绝缘膜。 接下来，通过湿法蚀刻去除位于与字线的端部相邻的侧壁绝缘膜的部分。 接下来，通过第二干蚀刻工艺去除位于字线形成区域周围的第一导电膜的一部分。 开口形成在第一导电膜中，使得在形成开口后残留的第一导电膜的一部分与形成在位于存储单元阵列外部的半导体衬底的有源区上的第二导电膜连续 形成区域以电连接到有源区域。

公开(公告)号：US06538937B2

公开(公告)日：2003-03-25

申请号：US09930968

申请日：2001-08-17

申请人： Takahiko Hashidzume ,  Yoshinori Odake

发明人： Takahiko Hashidzume ,  Yoshinori Odake

IPC分类号： G11C700

CPC分类号： G11C29/50 ,  H01L21/28273 ,  H01L27/11521

摘要： A circuit for testing a nonvolatile semiconductor memory includes a serial connection of flash memory cells as a first memory group. In the serial connection, the gates of the flash memory cells have been connected to each other, and a first one of the cells has its source or drain connected to the source or drain of a second one of the cells when the first and second cells are adjacent to each other.

公开(公告)号：US5510639A

公开(公告)日：1996-04-23

申请号：US384791

申请日：1995-02-09

申请人： Yasushi Okuda ,  Yoshinori Odake ,  Ichiro Nakao ,  Youhei Ichikawa

发明人： Yasushi Okuda ,  Yoshinori Odake ,  Ichiro Nakao ,  Youhei Ichikawa

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/06 ,  H01L29/788 ,  H01L29/76

CPC分类号： H01L29/66825 ,  H01L27/115 ,  H01L29/0692 ,  H01L29/7885

摘要： A non-volatile semiconductor memory cell having a novel structure is provided. The memory cell has a ring-shaped channel region formed on a semiconductor substrate, a drain region formed in a zone surrounded by the channel region, and a source region formed outside the channel region. The cell further includes a first gate insulation layer formed on the substrate in such a manner as to cover the boundary between the channel region and the drain region, a ring-shaped floating gate electrode formed on the first gate insulation layer, a second gate insulation layer formed on the floating gate electrode; and a control gate electrode which is capacitive-coupled with the floating gate via the second gate insulation layer.

摘要翻译： 提供具有新颖结构的非易失性半导体存储单元。 存储单元具有形成在半导体衬底上的环形沟道区域，形成在由沟道区域包围的区域中的漏极区域和形成在沟道区域外部的源极区域。 电池还包括以覆盖沟道区域和漏极区域之间的边界的方式形成在衬底上的第一栅极绝缘层，形成在第一栅极绝缘层上的环形浮栅电极，第二栅极绝缘层 形成在浮栅电极上的层; 以及通过第二栅极绝缘层与浮动栅极电容耦合的控制栅电极。

公开(公告)号：US6165825A

公开(公告)日：2000-12-26

申请号：US47353

申请日：1998-03-25

申请人： Yoshinori Odake

发明人： Yoshinori Odake

IPC分类号： H01L29/78 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

CPC分类号： H01L21/76216 ,  H01L21/823878

摘要： LOCOS layers for defining NMOSFET and PMOSFET forming regions Rn and Rp are formed, and then a protective oxide layer is formed. A first resist layer, opened above the region Rn, is then formed on the protective oxide layer. By using the first resist layer as a mask, ion implantation is performed twice to form a threshold control layer and a P- layer functioning as a punch-through stopper or the like. By using the first resist layer as a mask, the substrate is etched to remove a portion of the protective oxide layer. Then, the first resist layer is removed. These processes are also performed on the region Rp. Then, a gate oxide layer is formed. Thus, it is possible to prevent a foreign impurity, introduced during the ion implantation, from diffusing the surrounding regions when the resist layers are removed. As a result, the properties of the gate oxide layer can be improved.

摘要翻译： 形成用于定义NMOSFET和PMOSFET形成区域Rn和Rp的LOCOS层，然后形成保护性氧化物层。 然后在保护性氧化物层上形成在区域Rn上方开放的第一抗蚀剂层。 通过使用第一抗蚀剂层作为掩模，进行两次离子注入以形成阈值控制层和用作穿通塞子等的P-层。 通过使用第一抗蚀剂层作为掩模，蚀刻衬底以除去保护氧化物层的一部分。 然后，去除第一抗蚀剂层。 这些处理也在区域Rp上执行。 然后，形成栅氧化层。 因此，当去除抗蚀剂层时，可以防止在离子注入期间引入的异物杂质扩散周围区域。 结果，可以提高栅极氧化物层的性质。

公开(公告)号：US06274901B1

公开(公告)日：2001-08-14

申请号：US09477669

申请日：2000-01-05

申请人： Yoshinori Odake ,  Takashi Maejima ,  Hidenori Tanaka ,  Mitsuyoshi Andou

发明人： Yoshinori Odake ,  Takashi Maejima ,  Hidenori Tanaka ,  Mitsuyoshi Andou

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/7885

摘要： A stacked gate portion, including a tunnel insulating film, a floating gate electrode, a capacitive insulating film and a control gate electrode, is formed over a p-type Si substrate. In the p-type Si substrate, n++ source/drain layers and n+ source/drain layers, each layer containing arsenic, are formed. In the drain region, an n− drain layer, containing phosphorus and overlapping with an entire edge of the stacked gate portion in the gate width direction, and a p layer surrounding the bottoms of the n+ and the n− drain layers are provided. In such a structure, an electric field applied between the floating gate electrode and the drain is weakened and the drain-disturb characteristics are improved during writing.

摘要翻译： 在p型Si衬底上形成包括隧道绝缘膜，浮栅电极，电容绝缘膜和控制栅电极的层叠栅极部分。 在p型Si衬底中，形成n ++源极/漏极层和n +源极/漏极层，每个含有砷的层都形成。 在漏极区域中，设置有包含磷并且在栅极宽度方向上与堆叠栅极部分的整个边缘重叠的n沟道漏极层和围绕n +和n-drain层的底部的p层。 在这种结构中，在浮置栅电极和漏极之间施加的电场减弱，并且在写入期间漏极干扰特性得到改善。

公开(公告)号：US5715196A

公开(公告)日：1998-02-03

申请号：US684178

申请日：1996-07-19

申请人： Yoshinori Odake ,  Akira Asai ,  Yasushi Okuda ,  Toshiki Mori ,  Ichirou Nakao

发明人： Yoshinori Odake ,  Akira Asai ,  Yasushi Okuda ,  Toshiki Mori ,  Ichirou Nakao

IPC分类号： G11C16/04 ,  G11C16/26 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  G11C16/26 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/7883

摘要： An array of non-volatile memory cells arranged in rows and columns is provided. Each memory cell is composed of a transistor made up of a gate, a source, and drain and a capacitance section. Each memory cell is connected to a row decoder through a wordline, to a column decoder through a bitline, and to a source decoder through a sourceline. Arranged in a path extending from a bitline to a sourceline through a transistor is an anisotropic resistance section, e.g., a diode, exhibiting different voltage-current characteristics for different levels of voltages applied thereacross. Because of such arrangement, leakage current occurring to a deselected memory cell in a reading operation can be reduced or can be eliminated. Read errors due to leakage current can be avoided and the power consumption can be reduced.

摘要翻译： 提供了排列成行和列的非易失性存储单元阵列。 每个存储单元由由栅极，源极和漏极以及电容部分构成的晶体管构成。 每个存储单元通过字线连接到行解码器，通过位线连接到列解码器，并通过源线连接到源解码器。 在从位线延伸到源极线通过晶体管的路径中布置的是各向异性电阻部分，例如二极管，对于施加在其上的不同电压电平，具有不同的电压 - 电流特性。 由于这样的布置，可以减少或可以消除在读取操作中对取消选择的存储单元发生的泄漏电流。 可以避免由于泄漏电流而导致的读取错误，并且可以降低功耗。

公开(公告)号：US5627779A

公开(公告)日：1997-05-06

申请号：US505638

申请日：1995-07-21

申请人： Yoshinori Odake ,  Akira Asai ,  Yasushi Okuda ,  Toshiki Mori ,  Ichirou Nakao

发明人： Yoshinori Odake ,  Akira Asai ,  Yasushi Okuda ,  Toshiki Mori ,  Ichirou Nakao

IPC分类号： G11C16/04 ,  G11C16/26 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  G11C16/02

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  G11C16/26 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/7883

摘要： An array of non-volatile memory cells arranged in rows and columns is provided. Each memory cell is composed of a transistor made up of a gate, a source, and drain and a capacitance section. Each memory cell is connected to a row decoder through a wordline, to a column decoder through a bitline, and to a source decoder through a sourceline. Arranged in a path extending from a bitline to a sourceline through a transistor is an anisotropic resistance section, e.g., a diode, exhibiting different voltage-current characteristics for different levels of voltages applied thereacross. Because of such arrangement, leakage current occurring to a deselected memory cell in a reading operation can be reduced or can be eliminated. Read errors due to leakage current can be avoided and the power consumption can be reduced.

摘要翻译： 提供了排列成行和列的非易失性存储单元阵列。 每个存储单元由由栅极，源极和漏极以及电容部分构成的晶体管构成。 每个存储单元通过字线连接到行解码器，通过位线连接到列解码器，并通过源线连接到源解码器。 在从位线延伸到源极线通过晶体管的路径中布置的是各向异性电阻部分，例如二极管，对于施加在其上的不同电压电平，具有不同的电压 - 电流特性。 由于这样的布置，可以减少或可以消除在读取操作中对取消选择的存储单元发生的泄漏电流。 可以避免由于泄漏电流而导致的读取错误，并且可以降低功耗。

公开(公告)号：US07129135B2

公开(公告)日：2006-10-31

申请号：US11195652

申请日：2005-08-03

申请人： Yoshinori Odake

发明人： Yoshinori Odake

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11536

摘要： A first conductive film for forming a plurality of word lines is formed in a memory cell array formation region of a semiconductor substrate for a nonvolatile semiconductor memory device, and a second conductive film is formed in a semiconductor device formation region of the semiconductor substrate. Next, openings are formed in the first conductive film by a first dry etching process such that the word lines in the memory cell array formation region are located apart from one another. Thereafter, sidewall insulating films for the word lines are formed in the openings. Next, parts of the sidewall insulating films located adjacent to the ends of the word lines are removed by wet etching. Next, a part of the first conductive film located around a word line formation region is removed by a second dry etching process. The openings are formed in the first conductive film such that a part of the first conductive film remaining after the formation of the openings is continuous with the second conductive film, which is formed on an active region of the semiconductor substrate located outside the memory cell array formation region so as to be electrically connected to the active region.