公开(公告)号：US07247916B2

公开(公告)日：2007-07-24

申请号：US11267334

申请日：2005-11-07

申请人： Yoshio Ozawa ,  Masayuki Tanaka ,  Fumitaka Arai

发明人： Yoshio Ozawa ,  Masayuki Tanaka ,  Fumitaka Arai

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7883

摘要： The memory cell matrix encompasses (a) a plurality device isolation films running along column direction, (b) first conductive layers arranged along row and column-directions, adjacent groups of the first conductive layers are isolated from each other by the device isolation film disposed between the adjacent groups, (c) lower inter-electrode dielectrics arranged respectively on crests of the corresponding first conductive layers, (d) an upper inter-electrode dielectric arranged on the lower inter-electrode dielectric made of insulating material different from the lower inter-electrode dielectrics, and (e) second conductive layers running along the row-direction, arranged on the upper inter-electrode dielectric.

摘要翻译： 存储单元矩阵包括（a）沿着列方向延伸的多个器件隔离膜，（b）沿着行和列方向布置的第一导电层，相邻的第一导电层组通过设置的隔离膜相互隔离 （c）分别布置在相应的第一导电层的顶部上的下部电极间电介质，（d）布置在由绝缘材料制成的下部电极间电介质上的上部电极间电介质， - 电极介质，和（e）布置在上部电极间电介质上的沿着行方向延伸的第二导电层。

公开(公告)号：US07005714B2

公开(公告)日：2006-02-28

申请号：US10724103

申请日：2003-12-01

申请人： Yoshio Ozawa ,  Masayuki Tanaka ,  Fumitaka Arai

发明人： Yoshio Ozawa ,  Masayuki Tanaka ,  Fumitaka Arai

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7883

摘要： The memory cell matrix encompasses (a) a plurality device isolation films running along column direction, (b) first conductive layers arranged along row and column-directions, adjacent groups of the first conductive layers are isolated from each other by the device isolation film disposed between the adjacent groups, (c) lower inter-electrode dielectrics arranged respectively on crests of the corresponding first conductive layers, (d) an upper inter-electrode dielectric arranged on the lower inter-electrode dielectric made of insulating material different from the lower inter-electrode dielectrics, and (e) second conductive layers running along the row-direction, arranged on the upper inter-electrode dielectric.

公开(公告)号：US20050002231A1

公开(公告)日：2005-01-06

申请号：US10724103

申请日：2003-12-01

申请人： Yoshio Ozawa ,  Masayuki Tanaka ,  Fumitaka Arai

发明人： Yoshio Ozawa ,  Masayuki Tanaka ,  Fumitaka Arai

IPC分类号： G11C11/34 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7883

摘要： The memory cell matrix encompasses (a) a plurality device isolation films running along column direction, (b) first conductive layers arranged along row and column-directions, adjacent groups of the first conductive layers are isolated from each other by the device isolation film disposed between the adjacent groups, (c) lower inter-electrode dielectrics arranged respectively on crests of the corresponding first conductive layers, (d) an upper inter-electrode dielectric arranged on the lower inter-electrode dielectric made of insulating material different from the lower inter-electrode dielectrics, and (e) second conductive layers running along the row-direction, arranged on the upper inter-electrode dielectric.

摘要翻译： 存储单元矩阵包括（a）沿着列方向延伸的多个器件隔离膜，（b）沿着行和列方向布置的第一导电层，相邻的第一导电层组通过设置的隔离膜相互隔离 （c）分别布置在相应的第一导电层的顶部上的下部电极间电介质，（d）布置在由绝缘材料制成的下部电极间电介质上的上部电极间电介质， - 电极介质，和（e）布置在上部电极间电介质上的沿着行方向延伸的第二导电层。

公开(公告)号：US07387934B2

公开(公告)日：2008-06-17

申请号：US11267331

申请日：2005-11-07

申请人： Yoshio Ozawa ,  Masayuki Tanaka ,  Fumitaka Arai

发明人： Yoshio Ozawa ,  Masayuki Tanaka ,  Fumitaka Arai

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7883

摘要： The memory cell matrix encompasses (a) a plurality device isolation films running along column direction, (b) first conductive layers arranged along row and column-directions, adjacent groups of the first conductive layers are isolated from each other by the device isolation film disposed between the adjacent groups, (c) lower inter-electrode dielectrics arranged respectively on crests of the corresponding first conductive layers, (d) an upper inter-electrode dielectric arranged on the lower inter-electrode dielectric made of insulating material different from the lower inter-electrode dielectrics, and (e) second conductive layers running along the row-direction, arranged on the upper inter-electrode dielectric.

摘要翻译： 存储单元矩阵包括（a）沿着列方向延伸的多个器件隔离膜，（b）沿着行和列方向布置的第一导电层，相邻的第一导电层组通过设置隔离膜彼此隔离 （c）分别布置在相应的第一导电层的顶部上的下部电极间电介质，（d）布置在由绝缘材料制成的下部电极间电介质上的上部电极间电介质， - 电极介质，和（e）布置在上部电极间电介质上的沿着行方向延伸的第二导电层。

公开(公告)号：US20060060927A1

公开(公告)日：2006-03-23

申请号：US11267331

申请日：2005-11-07

申请人： Yoshio Ozawa ,  Masayuki Tanaka ,  Fumitaka Arai

发明人： Yoshio Ozawa ,  Masayuki Tanaka ,  Fumitaka Arai

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7883

摘要： The memory cell matrix encompasses (a) a plurality device isolation films running along column direction, (b) first conductive layers arranged along row and column-directions, adjacent groups of the first conductive layers are isolated from each other by the device isolation film disposed between the adjacent groups, (c) lower inter-electrode dielectrics arranged respectively on crests of the corresponding first conductive layers, (d) an upper inter-electrode dielectric arranged on the lower inter-electrode dielectric made of insulating material different from the lower inter-electrode dielectrics, and (e) second conductive layers running along the row-direction, arranged on the upper inter-electrode dielectric.

公开(公告)号：US20060054957A1

公开(公告)日：2006-03-16

申请号：US11267334

申请日：2005-11-07

申请人： Yoshio Ozawa ,  Masayuki Tanaka ,  Fumitaka Arai

发明人： Yoshio Ozawa ,  Masayuki Tanaka ,  Fumitaka Arai

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7883

摘要： The memory cell matrix encompasses (a) a plurality device isolation films running along column direction, (b) first conductive layers arranged along row and column-directions, adjacent groups of the first conductive layers are isolated from each other by the device isolation film disposed between the adjacent groups, (c) lower inter-electrode dielectrics arranged respectively on crests of the corresponding first conductive layers, (d) an upper inter-electrode dielectric arranged on the lower inter-electrode dielectric made of insulating material different from the lower inter-electrode dielectrics, and (e) second conductive layers running along the row-direction, arranged on the upper inter-electrode dielectric.

摘要翻译： 存储单元矩阵包括（a）沿着列方向延伸的多个器件隔离膜，（b）沿着行和列方向布置的第一导电层，相邻的第一导电层组通过设置的隔离膜相互隔离 （c）分别布置在相应的第一导电层的顶部上的下部电极间电介质，（d）布置在由绝缘材料制成的下部电极间电介质上的上部电极间电介质， - 电极介质，和（e）布置在上部电极间电介质上的沿着行方向延伸的第二导电层。

公开(公告)号：US20120112263A1

公开(公告)日：2012-05-10

申请号：US13351965

申请日：2012-01-17

申请人： Masayuki Tanaka ,  Daikuse Nishida ,  Ryota Fujitsuka ,  Katsuyuki Sekine ,  Akihito Yamamoto ,  Katsuaki Natori ,  Yoshio Ozawa

发明人： Masayuki Tanaka ,  Daikuse Nishida ,  Ryota Fujitsuka ,  Katsuyuki Sekine ,  Akihito Yamamoto ,  Katsuaki Natori ,  Yoshio Ozawa

IPC分类号： H01L29/788

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7883

摘要： A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film including a lower silicon nitride film, a lower silicon oxide film formed on the lower silicon nitride film, an intermediate insulating film formed on the lower silicon oxide film and containing a metal element, the intermediate insulating film having a relative dielectric constant of greater than 7, an upper silicon oxide film formed on the intermediate insulating film, and an upper silicon nitride film formed on the upper silicon oxide film.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的电荷存储层，形成在电荷存储层上的第二绝缘膜，以及形成在第二绝缘膜上的控制电极 ，所述第二绝缘膜包括下氮化硅膜，形成在所述下氮化硅膜上的下氧化硅膜，形成在所述下氧化硅膜上并含有金属元素的中间绝缘膜，所述中间绝缘膜具有相对电介质 大于7的常数，形成在中间绝缘膜上的上部氧化硅膜和形成在上部氧化硅膜上的上部氮化硅膜。

公开(公告)号：US07635890B2

公开(公告)日：2009-12-22

申请号：US11783934

申请日：2007-04-13

申请人： Yoshio Ozawa ,  Akihito Yamamoto ,  Masayuki Tanaka ,  Katsuaki Natori ,  Katsuyuki Sekine ,  Daisuke Nishida ,  Ryota Fujitsuka

发明人： Yoshio Ozawa ,  Akihito Yamamoto ,  Masayuki Tanaka ,  Katsuaki Natori ,  Katsuyuki Sekine ,  Daisuke Nishida ,  Ryota Fujitsuka

IPC分类号： H01L29/76

CPC分类号： H01L29/7883 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： A semiconductor device includes a semiconductor substrate, a plurality of nonvolatile memory cells provided on the semiconductor substrate, each of the plurality of nonvolatile memory cells comprising a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a control gate electrode provided above the charge storage layer, a second insulating film provided between the control gate electrode and the charge storage layer, the second insulating film between adjacent charge storage layers including a first region having permittivity lower than that of the second insulating film on a top surface of the charge storage layer in a cross-section view of a channel width direction of the nonvolatile memory cell, and the first region having composition differing from that of the second insulating film on the top surface of the charge storage layer.

摘要翻译： 半导体器件包括半导体衬底，设置在半导体衬底上的多个非易失性存储单元，所述多个非易失性存储单元中的每一个包括设置在所述半导体衬底上的第一绝缘膜，设置在所述第一绝缘膜上的电荷存储层， 设置在所述电荷存储层上方的控制栅电极，设置在所述控制栅电极和所述电荷存储层之间的第二绝缘膜，所述相邻电荷存储层之间的所述第二绝缘膜包括具有低于所述第二绝缘膜的介电常数的第一区域 在电荷存储层的顶表面上，以非易失性存储单元的沟道宽度方向的横截面视图，并且第一区域具有与电荷存储层的顶表面上的第二绝缘膜不同的组成。

公开(公告)号：US07544593B2

公开(公告)日：2009-06-09

申请号：US11999958

申请日：2007-12-07

申请人： Yoshitaka Tsunashima ,  Seiji Ihumiya ,  Yasumasa Suizu ,  Yoshio Ozawa ,  Kiyotaka Miyano ,  Masayuki Tanaka

发明人： Yoshitaka Tsunashima ,  Seiji Ihumiya ,  Yasumasa Suizu ,  Yoshio Ozawa ,  Kiyotaka Miyano ,  Masayuki Tanaka

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L21/82345 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/31604 ,  H01L21/823462 ,  H01L21/823475 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656

摘要： Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.

摘要翻译： 权利要求和公开的是一种半导体器件，包括具有在包含金属，硅和氧的金属硅酸盐的化合物中含有氮或氟的栅极绝缘膜结构的晶体管，具有非晶态金属氧化物层叠结构的栅极绝缘膜结构 膜和金属硅酸盐膜，或具有包括第一金属元素的氧化物膜的第一栅极绝缘膜和包括第二金属元素的金属硅酸盐膜的第二栅极绝缘膜的栅极绝缘膜结构。

公开(公告)号：US20080197403A1

公开(公告)日：2008-08-21

申请号：US12026942

申请日：2008-02-06

申请人： Yoshio OZAWA ,  Akihito Yamamoto ,  Katsuaki Natori ,  Masayuki Tanaka ,  Katsuyuki Sekine ,  Daisuke Nishida ,  Ryota Fujitsuka

发明人： Yoshio OZAWA ,  Akihito Yamamoto ,  Katsuaki Natori ,  Masayuki Tanaka ,  Katsuyuki Sekine ,  Daisuke Nishida ,  Ryota Fujitsuka

IPC分类号： H01L27/115

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/512 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7881

摘要： A semiconductor device includes a semiconductor substrate, and nonvolatile memory cells, each of the cells including a channel region having a channel length and a channel width, a tunnel insulating film, a floating gate electrode, a control gate electrode, an inter-electrode insulating film between the floating and control gate electrodes, and an electrode side-wall insulating film on side-wall surfaces of the floating and control gate electrodes, the electrode side-wall insulating film including first and second insulating films having first and second dielectric constants, the first dielectric constant being higher than the second dielectric constant, the second dielectric constant being higher than a dielectric constant of a silicon nitride film, the first insulating film being in a central region of a facing region between the floating and control gate electrodes, the second insulating region being in the both end regions of the facing region and protruding from the both end portions.

摘要翻译： 半导体器件包括半导体衬底和非易失性存储单元，每个单元包括具有沟道长度和沟道宽度的沟道区，隧道绝缘膜，浮栅电极，控制栅电极，电极间绝缘 在浮置控制栅电极和控制栅极电极的侧壁表面之间的电极侧壁绝缘膜，电极侧壁绝缘膜包括具有第一和第二介电常数的第一和第二绝缘膜， 所述第一介电常数高于所述第二介电常数，所述第二介电常数高于氮化硅膜的介电常数，所述第一绝缘膜位于所述浮动栅极和控制栅电极之间的面对区域的中心区域中， 第二绝缘区域位于面对区域的两端区域中并从两端口突出 ons。