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1.发明授权Hardware clipping device which compares objects with boundaries via use of absolute values 失效通过使用绝对值将对象与边界进行比较的硬件裁剪装置
公开(公告)号：US5982380A
公开(公告)日：1999-11-09
申请号：US929438
申请日：1997-09-16
CPC分类号： G06T15/30
摘要： It is judged that a vertex exists within a view volume when values stored in registers (231 to 236) are all "1". In other words, whether the vertex exists within or beyond the view volume can be judged by whether the values stored in the registers (231 to 236) are all "1" or not. To meet this requirement, a clip code generation/judgment unit (20) comprises a 6-input AND gate (24) which obtains a logical product of the values stored in the registers (231 to 236) to output a judgment signal (M1). With this configuration, a first step for clipping, i.e., the judgment on whether a primitive exists within or beyond a view volume is implemented in hardware, and thereby the operating speed is improved.
摘要翻译： 在存储在寄存器（231〜236）中的值全部为“1”的情况下，判断为在视野内存在顶点。 换句话说，可以通过存储在寄存器（231至236）中的值是否全部为“1”来判断顶点是否存在于视图体中或超出视图体积。 为了满足该要求，剪辑码生成/判断单元（20）包括6输入与门（24），其获得存储在寄存器（231至236）中的值的逻辑积，以输出判断信号（M1） 。 利用这种配置，在硬件中实现用于削波的第一步骤，即在视图体中或超过视图体积中是否存在基元的判断，从而提高了操作速度。
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2.发明授权Geometry processor capable of executing input/output and high speed geometry calculation processing in parallel 有权能够并行执行输入/输出和高速几何计算处理的几何处理器公开(公告)号：US06603481B1
公开(公告)日：2003-08-05
申请号：US09294002
申请日：1999-04-19
申请人： Hiroyuki Kawai , Robert Streitenberger , Yoshitsugu Inoue , Keijiro Yoshimatsu , Junko Kobara , Hiroyasu Negishi
发明人： Hiroyuki Kawai , Robert Streitenberger , Yoshitsugu Inoue , Keijiro Yoshimatsu , Junko Kobara , Hiroyasu Negishi
IPC分类号： G06F1580
CPC分类号： G06F15/8007
摘要： The geometry processor includes mutually independent first and second external interface ports connected to a host processor, and a rendering processor, respectively, and a geometry calculation core which processes a geometry calculation applied through the first external interface port from the host processor. The geometry calculation core includes a plurality of SIMD type floating point calculating units, a floating point power computing unit, an integer calculating unit, a controller responsive to an instruction from the host processor which controls the plurality of floating point calculating units, the floating point power computing unit and the integer calculating unit to process data from the host processor, and an output controller which outputs the processed data to the rendering processor through the second external interface port.
摘要翻译： 几何处理器包括分别连接到主机处理器和渲染处理器的相互独立的第一和第二外部接口端口以及处理通过第一外部接口端口从主机处理器应用的几何计算的几何计算核心。 几何计算核心包括多个SIMD型浮点计算单元，浮点计算单元，整数计算单元，响应于来自主处理器的控制多个浮点计算单元的指令的控制器，浮点 功率计算单元和用于处理来自主处理器的数据的整数计算单元，以及输出控制器，其通过第二外部接口端口将处理后的数据输出到渲染处理器。
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公开(公告)号：US06442627B1
公开(公告)日：2002-08-27
申请号：US09453547
申请日：1999-12-03
申请人： Hiroyasu Negishi , Junko Kobara , Yoshitsugu Inoue , Hiroyuki Kawai , Keijiro Yoshimatsu , Nelson Chan , Robert Streitenberger
发明人： Hiroyasu Negishi , Junko Kobara , Yoshitsugu Inoue , Hiroyuki Kawai , Keijiro Yoshimatsu , Nelson Chan , Robert Streitenberger
IPC分类号： G06F300
摘要： An output FIFO data transfer control device can comprise a geometric arithmetic core including one integer processing unit or IPU and a plurality of floating-point processing units or FPUs. Each processing unit includes an intermediate buffer or data output buffer for storing a data on an arithmetic result. When an instruction of data transfer from at least one of the plurality of processing units to one output FIFO is issued, a write/read pointer generating unit generates a write pointer identifying a specific location where data on an arithmetic result associated with the instruction is to be stored in the intermediate buffer of at least one of the plurality of processing units. The write/read pointer generating unit also generates a read pointer identifying a specific location where data is to be read out of the intermediate buffer of at least one of the plurality of processing units. A transfer mode setting unit sets a transfer mode identifying which at least one of the plurality of processing units is to transfer data on an arithmetic result, and sequentially furnishes a read enable signal to at least one of the plurality of processing units so as to read out the data from the intermediate buffer of at least one of the plurality of processing units.
摘要翻译： 输出FIFO数据传送控制装置可以包括包括一个整数处理单元或IPU以及多个浮点处理单元或FPU的几何运算核心。 每个处理单元包括用于存储关于算术结果的数据的中间缓冲器或数据输出缓冲器。 当发出从多个处理单元中的至少一个处理单元到一个输出FIFO的数据传送指令时，写入/读出指针生成单元产生一个写入指针，该指针识别与该指令相关联的算术结果的数据为 被存储在多个处理单元中的至少一个处理单元的中间缓冲器中。 写/读指针生成单元还生成识别要从多个处理单元中的至少一个的中间缓冲器读出数据的特定位置的读指针。 传送模式设置单元设置传送模式，其识别多个处理单元中的至少一个处理单元是在算术结果上传送数据，并且将读取使能信号顺序地提供给多个处理单元中的至少一个，以便读取 从多个处理单元中的至少一个的中间缓冲器输出数据。
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公开(公告)号：US06480873B1
公开(公告)日：2002-11-12
申请号：US09478004
申请日：2000-01-05
申请人： Yoshitsugu Inoue , Hiroyuki Kawai , Junko Kobara , Robert Streitenberger , Keijiro Yoshimatsu , Hiroyasu Negishi
发明人： Yoshitsugu Inoue , Hiroyuki Kawai , Junko Kobara , Robert Streitenberger , Keijiro Yoshimatsu , Hiroyasu Negishi
IPC分类号： G06F738
CPC分类号： G06F7/556
摘要： A power operation device comprises a bit operation unit or performing a bit shift operation on a logarithmic base bit string from a logarithm operation unit according to an input exponent bit string Y, and for furnishing the shifted logarithmic base bit string as a multiplication bit string. An exponent checking unit checks whether or not the input exponent bit string Y is the ith power of a base 2 where i is an integer, and, if so, furnishes a selection signal to direct selection of the multiplication bit string from the bit operation unit. A multiplication bit string selection unit selects and furnishes the multiplication bit string when it receives the selection signal from the exponent checking unit. In contrast, the multiplication bit string selection unit selects and furnishes another multiplication bit string from a multiplier otherwise. An exponential operation unit performs a base-2 exponential operation on the selected multiplication bit string from the multiplication bit string selection unit, i.e., computes 2Z where Z is the selected multiplication bit string, and furnishes the computed base-2 exponential value as the power operation-result XY.
摘要翻译： 电力操作装置包括位操作单元或者根据输入的指数位串Y从对数运算单元对对数基本位串执行位移操作，并将移位的对数基本位串提供为乘法位串。 指数检查单元检查输入指数位串Y是否是基数2的第i个幂，其中i是整数，如果是，则提供选择信号以从位操作单元直接选择乘法位串 。 乘法比特串选择单元当从指数检查单元接收到选择信号时，选择并提供乘法比特串。 相反，乘法比特串选择单元否则从乘数中选择并提供另一乘法比特串。 指数运算单元从乘法位串选择单元对所选择的乘法比特串执行基2指数运算，即计算2Z，其中Z是所选乘法位串，并将计算出的基2指数值作为幂 操作结果XY。
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公开(公告)号：US5974436A
公开(公告)日：1999-10-26
申请号：US954586
申请日：1997-10-20
CPC分类号： G06F7/556 , G06F7/5525 , G06F2207/5561
摘要： An execution processor that can carry out power calculation at high speed includes a base data register, an exponent data register, a multiplier, a multiplication input selector for selecting an input to the multiplier, first and second registers for storing a calculation result of the multiplier, a square root calculation unit, a square root calculation input selector for selecting an input to the square root calculation unit, a third register for storing a calculation result of the square root calculation unit, and a power calculation controller. The power calculation controller checks the integer region of the exponent data register for each bit while providing input/output control of the multiplication input selector, the first register, and the second register, and checks the decimal fraction region of the exponent data register for each bit to provide input/output control of the square root calculation input selector, the multiplication input selector, the first register, the second register, and the third register.
摘要翻译： 可以高速执行功率计算的执行处理器包括基本数据寄存器，指数数据寄存器，乘法器，用于选择到乘法器的输入的乘法输入选择器，用于存储乘法器的计算结果的第一和第二寄存器 平方根计算单元，用于选择对平方根计算单元的输入的平方根计算输入选择器，存储平方根计算单元的计算结果的第三寄存器和功率计算控制器。 功率计算控制器为每个位检查指数数据寄存器的整数区域，同时提供乘法输入选择器，第一寄存器和第二寄存器的输入/输出控制，并且为每个位检查指数数据寄存器的小数部分区域 位提供平方根计算输入选择器，乘法输入选择器，第一寄存器，第二寄存器和第三寄存器的输入/输出控制。
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6.发明授权公开(公告)号：US06711601B2
公开(公告)日：2004-03-23
申请号：US09775513
申请日：2001-02-05
IPC分类号： G06F7556
CPC分类号： G06F1/0307 , G06F1/035
摘要： A logarithmic arithmetic unit includes first logarithmic operation part multiplying an exponent part of floating-point data by a prescribed value, a logarithmic table memory outputting a logarithmic value corresponding to bit data expressing a digit higher than a prescribed digit of a fixed-point part of the floating-point data, divisional precision decision part deciding divisional precision on the basis of the exponent part, division part performing division on a dividend obtained by subtracting the bit data from the fixed-point part and a divisor of the bit data and obtaining a result of division of a number of digits set on the basis of the divisional precision, second logarithmic operation part obtaining the logarithmic value of a value obtained by dividing the fixed-point part by the bit data and sum operation part adding outputs from the first and second logarithmic operation parts and the logarithmic table memory to each other.
摘要翻译： 对数算术单元包括将浮点数据的指数部分乘以规定值的第一对数运算部，对数表存储器输出对应于与比特数据对应的对数值，比特数据表示高于定点部分的规定数位 所述浮点数据，分割精度判定部根据所述指数部判定分割精度，对所述定点部分减去所述位数据和所述位数据的除数进行除法而得到的除数， 基于分割精度设定的数位分割结果，第二对数运算部分求出通过将定点部分除以比特数据而获得的值的对数值和加法运算部分的加法运算部分，从第一和第 第二对数运算部分和对数表存储器。
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公开(公告)号：US07054979B2
公开(公告)日：2006-05-30
申请号：US09985009
申请日：2001-11-01
IPC分类号： G06F13/14
CPC分类号： H04L12/4625
摘要： The method of routing configuration accesses applied from the primary port to a plurality of secondary ports includes the steps of: distributing a plurality of configuration accesses received from the primary bus to the plurality of secondary ports in accordance with a predetermined algorithm, such that each of the devices on the secondary ports receives and responds to exactly a single access; and terminating configuration cycles after distributing the plurality of configuration accesses.
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8.发明授权公开(公告)号：US07038684B2
公开(公告)日：2006-05-02
申请号：US10200253
申请日：2002-07-23
申请人： Yoshitsugu Inoue , Hiroyuki Kawai , Junko Kobara , Yoshiyuki Kato
发明人： Yoshitsugu Inoue , Hiroyuki Kawai , Junko Kobara , Yoshiyuki Kato
CPC分类号： G06T15/005
摘要： An input section inputs vertex data from a host CPU or a geometry process section to a rendering main process section. The rendering main process section performs a rendering process in accordance with the vertex data inputted into the input section. Therefore, the host CPU can directly write the vertex data, which does not require a geometry process, to a rendering process apparatus and a processing speed of an overall graphics system can be thereby improved.
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9.发明申请公开(公告)号：US20060001670A1
公开(公告)日：2006-01-05
申请号：US11218774
申请日：2005-09-06
申请人： Yoshitsugu Inoue , Hiroyuki Kawai , Junko Kobara , Yoshiyuki Kato
发明人： Yoshitsugu Inoue , Hiroyuki Kawai , Junko Kobara , Yoshiyuki Kato
IPC分类号： G06T1/20
CPC分类号： G06T15/005
摘要： An input section inputs vertex data from a host CPU or a geometry process section to a rendering main process section. The rendering main process section performs a rendering process in accordance with the vertex data inputted into the input section. Therefore, the host CPU can directly write the vertex data, which does not require a geometry process, to a rendering process apparatus and a processing speed of an overall graphics system can be thereby improved.
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10.发明申请Assembler capable of reducing size of object code, and processor for executing the object code 审中-公开能够减少对象代码大小的汇编器和用于执行目标代码的处理器公开(公告)号：US20050108698A1
公开(公告)日：2005-05-19
申请号：US10841467
申请日：2004-05-10
IPC分类号： G06F9/45
CPC分类号： G06F8/4434
摘要： An instruction analyzing unit sequentially analyzes instructions of a program which is inputted to a program inputting unit. A NOP instruction analyzing part encodes continuous NOP instructions as one continuous NOP instruction. An instruction code outputting unit outputs the instruction encoded by the instruction analyzing unit as an object code. Therefore, the size of the object code can be reduced.
摘要翻译： 指令分析单元顺序地分析输入到程序输入单元的程序的指令。 NOP指令分析部分将连续的NOP指令编码为一个连续的NOP指令。 指令代码输出单元将由指令分析单元编码的指令作为目标代码输出。 因此，可以减少目标代码的大小。
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